TLK3118 Datasheet, PDF (42/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
DEVICE RESET REQUIREMENTS
Upon application of minimum valid power, the TLK3118 requires reset to be held for at least 10 µs. This allows
internal PLLs to stabilize (internal clocks) while internal digital logic is still held in reset. It is also required to
provision the HSTL driver controller using the procedure specified in Figure 24.
JITTER TEST PATTERN GENERATION AND VERIFICATION
Use one of the following procedures to generate and verify the respective jitter test pattern:
• High Frequency Test Pattern:
– Issue a hard or soft reset
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register to clear
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register and verify it is cleared. This indicates
that the RX link is up.
– Bypass the Lane Alignment by writing 1 to the RX Lane Align Bypass bit of the RX_BYPASS_CONTROL
register.
– Write “00” to the pattern_select field of the TEST_CONTROL register (4/5.25.1:0).
– Read the test pattern error counters for all channels (CHANNEL_0~3_ TEST_ERR_CNT), to clear the
counters.
– Start the pattern generation on the XAUI_TX and verification on the XAUI_RX by writing “1” to the
test_enable bit of the TEST_CONTROL register (4/5.25.2).
– At this point the pattern verification is in progress and the errors are reported in the error counters.
– Reading the counters has no effect on the test except clearing them, i.e. the verification of the pattern
continues until the test_enable bit of the TEST_CONTROL register is cleared.
• Low Frequency Test Pattern:
– Issue a hard or soft reset.
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register to clear.
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register and verify it is cleared. This indicates
that the RX link is up.
– Bypass the Lane Alignment by writing 1 to the RX Lane Align Bypass bit of the RX_BYPASS_CONTROL
register.
– Write “01” to the pattern_select field of the TEST_CONTROL register (4/5.25.1:0).
– Read the test pattern error counters for all channels (CHANNEL_0~3_ TEST_ERR_CNT), to clear the
counters.
– Start the pattern generation on the XAUI_TX and verification on the XAUI_RX by writing “1” to the
test_enable bit of the TEST_CONTROL register (4/5.25.2).
– At this point the pattern verification is in progress and the errors are reported in the error counters.
– Reading the counters has no effect on the test except clearing them, i.e. the verification of the pattern
continues until the test_enable bit of the TEST_CONTROL register is cleared.
• Mixed Frequency Test Pattern:
– Issue a hard or soft reset.
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register to clear.
– Read the RX Local Fault bit (4/5/8.10) of the XS_STATUS_2 register and verify it is cleared. This indicates
that the RX link is up.
– Bypass the Lane Alignment by writing 1 to the RX Lane Align Bypass bit of the RX_BYPASS_CONTROL
register.
– Write “10” to the pattern_select field of the TEST_CONTROL register (4/5.25.1:0).
– Read the test pattern error counters for all channels (CHANNEL_0~3_ TEST_ERR_CNT), to clear the
counters.
– Start the pattern generation on the XAUI_TX and verification on the XAUI_RX by writing “1” to the
test_enable bit of the TEST_CONTROL register (4/5.25.2).
– At this point the pattern verification is in progress and the errors are reported in the error counters.
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