TLK3118 Datasheet, PDF (14/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
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DET3
During this state, the alignment character code detect circuit is active on each channel but the column
re-alignment is disabled. The column state machine will remain in this state looking for a column of alignment
character codes. If an incomplete alignment column is detected (alignment character codes not found on all
channels) or a deskew error is detected, the column state machine will transition to state UNALIGN. While in this
state, the Column Alignment Sync bit is set to '0' in MDIO registers 4:5.24.12 indicating the column is not aligned.
Detection of a complete alignment column will cause the column state machine to transition to state ALIGN.
NOTE:
The XGXS Lane Alignment bit = '0' will cause a local fault to be output on the receive
data bus.
ALIGN
This is the normal state for receiving data. When in this state, the column state machine will set the Column
Alignment Sync bit to '1' in MDIO registers 4:5.24.12 indicating that all channels are aligned. During this state the
alignment character code detect circuit is active on each channel but the column re-alignment is disabled. If a
deskew error is detected in the correct position within the Inter-Packet Gap, the column state machine will
transition to state FAIL1.
FAIL1
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4:5.24.12. During this state the
alignment character code detect circuit is active on each channel but the column re-alignment is disabled. If a
complete alignment column is not detected in the correct position within the Inter-Packet Gap, the column state
machine will transition to state FAIL2.
FAIL2
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4:5.24.12. During this state the
alignment character code detect circuit is active on each channel but the column re-alignment is disabled. If a
complete alignment column is not detected in the correct position within the Inter-Packet Gap, the column state
machine will transition to state FAIL3.
FAIL3
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4:5.24.12. During this state the
alignment character code detect circuit is active on each channel but the column re-alignment is disabled. If
complete alignment column is not detected in the correct position within the Inter-Packet Gap, the column state
machine will transition to state UNALIGN.
Inter-Packet Gap Management
When in transceiver mode, the TLK3118 replaces the idle codes (see Table 2) during the Inter-Packet Gap (IPG)
with the necessary codes to perform all channel alignment, byte alignment, and clock tolerance compensation as
defined in IEEE 802.3ae 10Gbps Ethernet Standard. According to the Ethernet Standard, a valid packet must
begin on TXD(0:7) of the XGMII. However, due to variable packet sizes, the IPG can begin on any channel. The
TLK3118 will replace idle codes latched on the same XGMII clock edge as the end of packet code with /K/ codes
(as shown in Figure 13).
14