TLK3118 Datasheet, PDF (7/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Detailed Description (continued)
Parallel Interface Data
Data placed on the XGMII transmit input bus is latched on the rising and falling edge of the transmit data clock,
TCLK, as shown in Figure 6. The latched data is then phase aligned to the internal version of the transmit
reference clock, 8b/10b encoded, serialized, then transmitted sequentially beginning with the LSB of the encoded
data byte over the differential high speed serial transmit pins.
The XGMII receive data bus outputs four bytes on RXD (31:0). Control character (K-characters) reporting for
each byte is done by asserting the corresponding control pin, RXC (3:0). When RXC is asserted, the 8 bits of
data corresponding to the control pin is to be interpreted as a K-character. If an error is uncovered in decoding
the data, the control pin is asserted and 0xFE is output for the corresponding byte.
Transmission Latency
For each channel, the data transmission latency of the TLK3118 is defined as the delay from the rising or falling
edge of the selected transmit clock when valid data is on the transmit data pins to the serial transmission of bit 0,
as shown in the following figure. The maximum transmit latency (TLATENCY ) is 600 bit times; the standard
allows a combined latency (TX + RX) of 2048 bit times.
TXxP
TXxN
TXD[0−31]
t_{d(T_Latency)}
Byte to be Transmitted
10 Bit Code Transmitted
TCLK
Figure 8. Transmission Latency
Channel Clock to Serial Transmit Clock Synchronization
The TLK3118 allows ±200 ppm difference between the serdes transmit reference on the XAUI side, versus the
input TCLK on the XGMII side. There exists a FIFO capable of CTC operations, and has a depth of 32 locations
(32 bits wide per location).
The reference clock and the transmit data clock(s) may be from a common source, but the design allows for up
to +/- 200 ppm of frequency difference should the application require it.
Data Reception Latency
For each serial link, the serial-to-parallel data latency is the time from when the first bit arrives at the serial
receiver input until it is output in the aligned parallel word on the XGMII, as shown in Figure 9. The maximum
receive latency (RLATENCY) is 700 bit times; the standard allows a combined latency (TX + RX) of 2048 bit
times.
RDP
RDN
RXD[0−31]
10 Bit Code Received
t_{d(R_Latency)}
Byte Received
RCLK
Figure 9. Receiver Latency
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