TLK3118 Datasheet, PDF (24/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
MDC
MDIO
32 “1”s
Hi-Z
0
0
1
1
A4
A0 DA4 DA0
0
D15 D0
1
Preamble
Start
Read Code
PHY Address
Dev Address
Data
Idle
Turn Around
Figure 25. Management Interface Extended Space Read Timing
MDC
MDIO
32 “1”s
Hi-Z
0
0
1
0
A4
A0 DA4 DA0
0
D15 D0
1
Preamble
Start
PHY Address
Read and Inc Code
Dev Address
Data
Idle
Turn Around
Figure 26. Management Interface Extended Space Read and Increment Timing
The IEEE 802.3 Clause 45 specification defines many of the registers, and additional registers have been
implemented for expanded functionality.
PROGRAMMER'S REFERENCE
Table 6. XS⁽¹⁾_CONTROL_1
Bit(s)
4/5.0.15
4/5.0.14
4/5.0.13
4/5.0.11
4/5.0.6
4/5.0.5:2
Address:0x0000
Default:0x2040
Name
Description
Reset
1 = XS reset (including all registers)
0 = Normal operation
Loop back
1 = Enable loop back mode.
If the device is configured as PHY XS (DVAD(0) = 1), then
XAUI_LOOPBACK will be performed (RX parallel to TX parallel)
If the device is configured as DTE XS (DVAD(0) = 0), then
XGMII_LOOPBACK will be performed (TX serial to RX serial)
0 = Disable loop back mode
Speed Selection
This bit always reads 1 indicating operation at 10 Gb/s and above.
Low power
1 = Low power mode
0 = Normal operation
Speed Selection
This bit always reads 1 indicating operation at 10Gbps and above.
Speed Selection
These bits always read 0 indicating operation at 10Gbps.
(1) In this section XS refers to either PHY or DTE XS device.
(2) RO: Read-Only , RW: Read-Write, SC: Self-Clearing, LL: Latching-Low, LH: Latching-High, COR: Clear-on-Read
Bit(s)
4/5.1.7
Fault
Table 7. XS_STATUS_1
Address:0x0001
Default:0x0082
Name
Description
1 = Fault condition detected (either on TX or RX side. This bit is ORed
version of 4/5.8.10 and 4/5.8.11)
0 = No fault condition detected
Access ⁽²⁾
RW
SC
RW
Access
RO
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