TLK3118 Datasheet, PDF (36/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
The slew rate of the differential driver may be controlled to suit different transmission media and data rates. This
is controlled through CFG [16:15] and CFG [6:5], the effects are shown in the previous table.
CFG[16:15]
00
01
10
11
Table 60. Slew Rate Control, Tx Rise and Fall Times
CFG[6:5] = 01 or 10
MIN
MAX
90 ps
90 ps
146 ps
146 ps
173 ps
173 ps
281 ps
281 ps
MIN
90 ps
101 ps
126 ps
144 ps
CFG[6:5] = 00
MAX
104 ps
145 ps
169 ps
196 ps
Table 61. SERDES_CONFIG_2
Address:0x8085
Default:0x0A00
Bit(s)
Name
Description
4/5.32901.15 JNCSEL (CFG[7])
0 = JOGCOM[0..7] controls whether comma alignment is enabled on lane
0..7 (Default)
1 = JOGCOM[0..7] induces an alignment jog on lane 0..7
4/5.32901.14: DATARATE (CFG[6:5])
13
00 = Full Rate (Default)
01 = Half Rate
10 = Quarter Rate
11 = Reserved
4/5.32901.12 EN8 (CFG[4])
0 = 10 bit operation (Default)
1 = 8 bit operation
4/5.32901.11 PLL_LBW (CFG[3])
0 = High loop bandwidth
1 = Low loop bandwidth (Default)
4/5.32901.10: PLLMUL (CFG[2:0])
8
PLL multiply factor. Can be calculated from following equation.
REFCLK
(freq)
+
LINERATE
PLLMULTIPLY
2
000 = 5x
001 = 25x
010 = 10x (Default)
011 = 15x
100 = 4x
101 = 20x
110 = 8x
111 = Reserved
Access
RW
Table 62. SERDES_DATA_CONTROL⁽¹⁾
Address:0x8086
Default:0xFFFF
Bit(s)
Name
Description
4/5.32902.15: Enable TX
8
1 = Transmit data pair is enabled for channels 7~0
0 = Transmit data pair is disabled for channels 7~0 (Bit 15 corresponds to
channel 7)
4/5.32902.7:0 Enable RX
1 = Receive data pair is enabled for channels 7~0
0 = Receive data pair is disabled for channels 7~0 (Bit 7 corresponds to
channel 7 )
Access
RW
(1) When power down mode is enabled using Control register (4/5.0), the SERDES macros go into power down mode where the TX and
RX data pairs are disabled for all channels. When A side is powered down, TX and RX data pairs are disabled for channels 3~0. When
B side is powered down TX and RX data pairs are disabled for channels 7~4. These low-power modes override the settings in this
register. Bits 11:8 corresponds to A side and bits 15:12 corresponds to B side of TX path. Bits 3:0 corresponds to A side and bits 7:4
corresponds to B side of RX path. In normal mode(A side as primary channel, A_B = 1) all the bits needs to be enabled for the normal
operation and when B side acts as primary channel(A_B = 0), A side bits can be disabled.
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