TLK3118 Datasheet, PDF (34/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
Table 55. LANE_3_ERROR_CODE
Address:0x8025
Default:0x0800
Bit(s)
Name
Description
4/5.32805.15: Lane 3 error code select
7
Error code to be transmitted in case of error condition. This applies to both
TX and RX data paths. The msb is the control bit; remaining 8 bits constitute
the error code. The default value for lane 3 corresponds to 8’h01 with the
control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF||
Access
RW
Table 56. RX_PHASE_SHIFT_CONTROL
Address:0x8026
Default:0x0000
Bit(s)
Name
Description
4/5.32806. 15 Lane 3 phase shift
When set, delays the RX data sent to the XGMII interface by one clock cycle
4/5.32806. 14 Lane 2 phase shift
4/5.32806. 13 Lane 1 phase shift
4/5.32806. 12 Lane 0 phase shift
Access
RW
Table 57. CHANNEL_SYNC_CONTROL
Address:0x8027
Default:0x0000
Bit(s)
Name
Description
4/5.32807. 15 Lane 3 channel sync bypass When set, lane synchronization for the corresponding lane is bypassed.
4/5.32807. 14 Lane 2 channel sync bypass
4/5.32807. 13 Lane 1 channel sync bypass
4/5.32807. 12 Lane 0 channel sync bypass
4/5.32807. 11 Lane 3 channel sync freeze When set, freezes the last acquired word alignment for the corresponding
4/5.32807. 10 Lane 2 channel sync freeze ^lane.
4/5.32807. 9 Lane 1 channel sync freeze
4/5.32807. 8 Lane 0 channel sync freeze
Access
RW
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