TLK3118 Datasheet, PDF (41/57 Pages) Texas Instruments – Redundant XAUI Transceiver

www.ti.com
TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
7. Repeat the previous step 64 more times (this toggles the CLK for both macros for 64 cycles). In the first 32
cycles, N1 through N5 bits in the macros are set from bits 11 through 15 of VTP1_BIT_CONTROL and
VTP2_BIT_CONTROL registers. In the second 32 cycles, P1 through P5 bits in the macros are set from bits
6 through 10 of VTP1_BIT_CONTROL and VTP2_BIT_CONTROL registers for the corresponding macro.
8. Toggle the CLK for one more cycle (Write 0xEE00 followed by 0xAA00).
9. Write 0xBB20 to lock the macro settings and also enable the switching activity on the outputs.
CLK
(VTP_MACRO_CONTROL[14/10]
¡¡¡¡
¡¡¡¡ _CLRZ
¡¡ (VTP_MACRO_CONTROL[13/9]
¡¡¡¡¡¡
EN
(VTP_MACRO_CONTROL[15/11]
NCH VTP bits set
(32 clock cycles)
N1, N2, N3, N4, N5
PCH VTP bits set
(32 clock cycles)
P1, P2, P3, P4, P5
¡¡¡¡
LOCK
(VTP_MACRO_CONTROL[12/8]
VTP outputs reset
Figure 27. Typical Procedure for Setting Driver Output Impedance
Table 78. VTP2_BIT_CONTROL⁽¹⁾
Bit(s)
4/5.32922.15
4/5.32922.14
4/5.32922.13
4/5.32922.12
4/5.32922.11
4/5.32922.10
4/5.32922.9
4/5.32922.8
4/5.32922.7
4/5.32922.6
N1IN
N2IN
N3IN
N4IN
N5IN
P1IN
P2IN
P3IN
P4IN
P5IN
Address:0x809A
Name
Description
N1 signal to be loaded when VTP2 EN = 0
N2 signal to be loaded when VTP2 EN = 0
N3 signal to be loaded when VTP2 EN = 0
N4 signal to be loaded when VTP2 EN = 0
N5 signal to be loaded when VTP2 EN = 0
P1 signal to be loaded when VTP2 EN = 0
P2 signal to be loaded when VTP2 EN = 0
P3 signal to be loaded when VTP2 EN = 0
P4 signal to be loaded when VTP2 EN = 0
P5 signal to be loaded when VTP2 EN = 0
(1) See procedure for setting the drive strength values for the VTP macros in page 61.
Default:0xA0C0
Access
RW
OPERATING FREQUENCY RANGE
The TLK3118 is optimized for operation at a serial data rate of 3.125 Gbit/s. The external differential reference
clock has an operating frequency of 156.25 MHz. The reference clock frequency must be within ±200 PPM and
have less than 40 ps of jitter.
POWERDOWN MODE
The TLK3118 (through both register I/O and pin control) is capable of going into a low power quiescent state. In
this state, all analog and digital circuitry is disabled.
41