TLK3118 Datasheet, PDF (32/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 44. RX_CTC_STATUS
Bit(s)
4/5.32794.9
4/5.32794.8
4/5.32794.7
4/5.32794.6
4/5.32794.5
4/5.32794.4
4/5.32794.3
4/5.32794.2
4/5.32794.1
4/5.32794.0
Address:0x801A
Default:0x0000
Name
Description
Lane 3 overflow
When high, indicates overflow error in the corresponding lane.
Lane 2 overflow
Lane 1 overflow
Lane 0 overflow
Lane 3 underflow
When high, indicates underflow error in the corresponding lane.
Lane 2 underflow
Lane 1 underflow
Lane 0 underflow
Overflow
When high, indicates overflow error in any lane.
Underflow
When high, indicates underflow error in any lane.
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Access
RO/LH
Table 45. RX_CTC_INSERT_COUNT
Address:0x801B
Bit(s)
Name
Description
4/5.32795.15: Idle insert count
0
Counter for number of idle insertions in RX side
Default:0xFFFD
Access
RO/COR
Table 46. RX_CTC_DELETE_COUNT
Address:0x801C
Bit(s)
Name
Description
4/5.32796.15: Idle delete count
0
Counter for number of idle deletions
Default:0xFFFD
Access
RO/COR
Bit(s)
4/5.32797.3
4/5.32797.2
4/5.32797.1
4/5.32797.0
Table 47. DATA_DOWN
Address:0x81D
Default:0x0000
Name
Description
Lane 3 data down
Lane 2 data down
Lane 1 data down
When high, indicates that link for the corresponding lane was inactive (data
did not toggle) for 4095 cycles of 312.5-MHz clock.
The 312.5 MHz is generated internally by the PLL from the 156-MHz
Reference clock.
Lane 0 data down
Access
RO/COR
Table 48. RX_BYPASS_CONTROL
Bit(s)
4/5.32798.15
4/5.32798.14
4/5.32798.11
4/5.32798.10
4/5.32798.9
4/5.32798.8
4/5.32798.7
4/5.32798.3
Address:0x801E
Default:0x0000
Name
Description
RX CTC bypass
When set, bypasses clock tolerance compensation on the RX side
IPG Checker bypass
When set, bypasses the replacement of /A/K/R/ into Idles and also bypasses
end-of-packet error checking.
Lane 3 8B/10B decoder by- When set, disables the 8B/10B decoding for the corresponding lane
pass
Lane 2 8B/10B decoder by-
pass
Lane 1 8B/10B decoder by-
pass
Lane 0 8B/10B decoder by-
pass
Consider sequence column When set, sequence columns are counted as part of IPG
part of IPG
When low, sequence columns are not counted as IPG
RX Lane align bypass
When set, bypasses lane alignment on the RX side
Access
RW
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