TLK3118 Datasheet, PDF (43/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
– Reading the counters has no effect on the test except clearing them, i.e. the verification of the pattern
continues until the test_enable bit of the TEST_CONTROL register is cleared.
• Continuous Random Test Pattern (CRPAT):
– Issue a hard or soft reset.
– Read the test pattern error counter cr_cj_err_cnt registers (4/5.32278 – 4/5.32279) to clear.
– Write “1” to the crpat_enable bit of the Vendor Specific TEST_CONFIG register (4/5.32768.1).
– Enable the CRPAT verifier by writing 1 to CRPAT Check Enable bit of the
TEST_VERIFICATION_CONTROL register (4/5.32769.1).
– In order for the Test Pattern Verifier to start checking the test pattern, it has to receive the Preamble /SFD
that is sent at every packet from the test pattern generator. To make sure that the test pattern checking
has started, read the 4/5/32801.15 (Test Pattern Status) bit of the Test Pattern Verification Status register.
Make sure that the Test Pattern Sync bit is HIGH. If the sync status is not high, this indicates that the
verifier never received the Preamble, which may indicate a more severe link problem.
– Perform the test as long as desired.
– Read the CRPAT_CJPAT_TEST_ERROR_COUNT register. Any subsequent counter reads are invalid. If
additional reads are required they must be done in separate tests.
– If another test is to be performed go to the first step.
• Continuous Jitter Test Pattern (CJPAT):
– Issue a hard or soft reset.
– Read the test pattern error counter cr_cj_err_cnt registers (4/5.32278 – 4/5.32279) to clear.
– Write “1” to the cjpat_enable bit of the Vendor Specific TEST_CONFIG register (4/5.32768.0).
– Enable the CJPAT verifier by writing 1 to CJPAT Check Enable bit of the
TEST_VERIFICATION_CONTROL register (4/5.32769.0).
– In order for the Test Pattern Verifier to start checking the test pattern, it has to receive the Preamble /SFD
that is sent at every packet from the test pattern generator. To make sure that the test pattern checking
has started, read the 4/5/32801.15 (Test Pattern Status) bit of the Test Pattern Verification Status register.
Make sure that the Test Pattern Sync bit is HIGH. If the sync status is not high, this indicates that the
verifier never received the Preamble, which may indicate a more severe link problem.
– Perform the test as long as desired.
– Read the CRPAT_CJPAT_TEST_ERROR_COUNT register. Any subsequent counter reads are invalid. If
additional reads are required they must be done in separate tests.
– If another test is to be performed go to the first step.
If more than one test is specified results are unpredictable.
TERMINAL
NAME
NO.
REFCLKP/
REFCLKN
R9,R10
TCLK
F2
RCLK
E20
DEVICE INFORMATION
XGMII
NAME
N/A
TX_CLK
RX_CLK
Table 79. CLOCK PINS
TYPE
DESCRIPTION
DPECL Input
HSTL/ Input
HSTL/ Output
Differential Reference Input Clock This differential pair accepts DPECL
compatible signals. AC coupling is required. An on-chip 100-Ω termination
resistor is placed differentially between the pins. No external biasing is required.
This clock is 156.25 MHz ± 200 ppm
Transmit Data Clock This is the input 156.25-MHz ±200 ppm XGMII transmit
data path clock input. It is used to sample TXD (31:0), and TXC (3:0).
Receive Data Clock This is the output 156.25-MHz ±200 ppm XGMII receive
data path clock output. This clock is centered in the middle of the DDR RXD
(31:0) and RXC (3:0) data output pins.
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