TLK3118 Datasheet, PDF (33/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 49. CLOCK_DOWN_STATUS
Bit(s)
4/5.32799. 7
4/5.32799. 6
4/5.32799. 5
4/5.32799. 4
4/5.32799. 3
4/5.32799. 2
4/5.32799. 1
4/5.32799. 0
Address:0x801F
Default:0x0000
Name
Description
Lane 3 clock 312 down
Lane 2 clock 312 down
Lane 1 clock 312 down
When high, indicates that 312-MHz clock is down on the corresponding lane
for 255 or more cycles. The detection is done on the transmit side.
The 312.5MHz is generated internally by the PLL from the 156-MHz
Reference clock.
Lane 0 clock 312 down
Lane 3 clock 156 down
Lane 2 clock 156 down
When high, indicates that 156-MHz XGMII clock is down on the correspond-
ing lane for 255 or more cycles. The detection is done on the transmit side.
Lane 1 clock 156 down
Lane 0 clock 156 down
Access
RO/LH
Table 50. AUXILIARY_RESET_CONTROL
Address:0x8020
Default:0x0000
Bit(s)
Name
Description
4/5.32800. 15 Transmit auxiliary reset
When set, resets XAUI transmit data path but does not reset any R/W
registers.
4/5.32800. 14 Receive auxiliary reset
When set, resets XAUI receive data path but does not reset any R/W
registers.
4/5.32800. 13 TLK3118 auxiliary reset
When set, resets the DDR, RETIME muxing, A/B muxing logic but does not
reset any R/W registers.
Access
RW/SC
Table 51. TEST_PATTERN_STATUS
Bit(s)
4/5/32801.15
Address:0x8021
Default:0x0000
Name
Description
Test pattern sync status
When high, indicates that preamble for CRPAT/CJPAT has been recovered.
Access
RO
Table 52. LANE_0_ERROR_CODE
Address:0x8022
Default:0xCE00
Bit(s)
Name
Description
4/5.32802.15: Lane 0 error code select
7
Error code to be transmitted in case of error condition. This applies to both
TX and RX data paths. The msb is the control bit; remaining 8 bits constitute
the error code. The default value for lane 0 corresponds to 8’h9C with the
control bit being 1’b1. The default values for lanes 0~3 correspond to ||LF||
Access
RW
Table 53. LANE_1_ERROR_CODE
Address:0x8023
Default:0x0000
Bit(s)
Name
Description
4/5.32803.15: Lane 1 error code select
7
Error code to be transmitted in case of error condition. This applies to both
TX and RX data paths. The msb is the control bit; remaining 8 bits constitute
the error code. The default value for lane 1 corresponds to 8’h00 with the
control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF||
Access
RW
Table 54. LANE_2_ERROR_CODE
Address:0x8024
Default:0x0000
Bit(s)
Name
Description
4/5.32804.15: Lane 2 error code select
7
Error code to be transmitted in case of error condition. This applies to both
TX and RX data paths. The msb is the control bit; remaining 8 bits constitute
the error code. The default value for lane 2 corresponds to 8’h00 with the
control bit being 1’b0. The default values for lanes 0~3 correspond to ||LF||
Access
RW
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