TLK3118 Datasheet, PDF (35/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 58. SERDES_CONFIG_1⁽¹⁾
Address:0x8084
Default:0x802C
Bit(s)
Name
Description
4/5.32900.15 TXBCLKM CFG[23]
0 = Individual lane TXBCLK ports are used
1 =TXBCLK[1] is used to time TD for all lanes (default)
4/5.32900.14: Pre emphasis (CFG[22:19])
11
Refer Table 59: Transmit Pre-emphasis Settings
Depends on transmit swing setting controlled by CFG [18:17]. These bits do
not have any effect if CFG[18:17] = 2’b10 (Default 4’b0000)
4/5.32900.10: SWING (CFG[18:17])
9
Output swing setting
00 = Maximum transmit amplitude, pre-emphasis available (Default)
01 = 62.5% transmit amplitude, increased pre-emphasis available
10 = 37.5% transmit amplitude, pre-emphasis unavailable
11 = 0% transmit amplitude
4/5.32900.8:7 Slew Rate (CFG[16:15])
Slew Rate setting
Refer Table 60: Slew rate control. Tx Rise and Fall times
00 = Fastest edge rate, independent of DATARATE (Default)
01 = Intermediate edge rate for given DATARATE
10 = Slower intermediate edge rate for given DATARATE
11 = Slowest edge rate for given DATARATE
4/5.32900.6 EXTREF (CFG[14])
4/5.32900.5 AC Coupled (CFG[13])
0 = Internally generated reference is used to set output amplitude
1 = External reference VREF is used to set output amplitude
TI recommends using external V_ref with V_ref = V_DDT - 0.8 V
0 = AC coupled operation is disabled
1 = AC coupled operation is enabled (Default)
4/5.32900.4 Enable LOL (CFG[12])
0 = Loss of link detection is disabled (Default)
1 = Loss of link detection is enabled
4/5.32900.3 FASTEQ (CFG[11])
0 = Adaptive equalization set on low data rate
1 = Adaptive equalization set on high data rate (Default)
4/5.32900.2 ENEQ (CFG[10])
0 = Adaptive equalization is disabled
1 = Adaptive equalization is enabled (Default)
4/5.32900.1 FASTUPDT (CFG[9])
0 = Fast update mode is disabled (Default)
1 = Fast update mode is enabled
4/5.32900.0 FASTLOCK (CFG[8])
0 = Fast-lock mode is disabled (Default)
1 = Fast-lock mode is enabled
Access
RW
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values. They can be accessed from A
side or B side.
Mode
Disabled
1 – Tap
2 – Tap
Table 59. Transmit Pre-emphasis Settings
CFG[22:19]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
100% Swing
1^st Bit
2^nd Bit
0%
0%
5%
0%
11%
0%
18%
0%
25%
0%
33%
0%
43%
0%
67%
0%
100%
0%
25%
18%
33%
18%
33%
25%
43%
25%
54%
25%
82%
54%
100%
54%
62.5% Swing
1^st Bit
2^nd Bit
0%
0%
9%
0%
19%
0%
32%
0%
47%
0%
67%
0%
92%
0%
178%
0%
400%
0%
47%
32%
67%
32%
67%
47%
92%
47%
127%
47%
257%
127%
400%
127%
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