TL16PIR552 Datasheet, PDF (8/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
The receiver-FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
SINx
RTSx
Start Byte N _Stop
Start Byte N+1 _Stop
Start Byte _Stop
IOR
(IOR RBR)
1
2
N
N+1
NOTES: A. N = RCV-FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 3. RTS Functional Timing, RCV-FIFO Trigger Level = 1,4, or 8 Bytes
SINx
RTSx
Byte 14
Byte 15
Start Byte 16 Stop
RTS Released After the
First Data Bit of Byte 16
Start Byte 18 Stop
IOR
(IOR RBR)
NOTE A: RTSx is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth
byte. RTSx is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more
than one byte of space available. When the receive FIFO is full, the first receive buffer-register read reasserts RTSx.
Figure 4. RTS Functional Timing, Receiver - FIFO Trigger Level = 14 Bytes
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input voltage range, V_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V_CC + 0.5 V
Output voltage range, V_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) (See Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) (See Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, level shift, I_OK (V_O < 0 or V_O > V_CC) (See Note 3) . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Virtual junction, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. This applies to external input and bidirectional buffers. VI < VCC does not apply to fail-safe terminals.
3. This applies to external output and bidirectional buffers. VO < VCC does not apply to fail-safe terminals.
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