TL16PIR552 Datasheet, PDF (49/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
EPP mode
When the EPP mode is selected in the configuration register, the standard and bidirectional modes are also
available. If no EPP read, write, or address cycle is currently executing, then the PDx bus is in the standard or
bidirectional mode. All output signals (STROBE, AUTOFD, INIT) are set by the device control register and the
direction is controlled by the DIR of the control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a timer is required to
prevent system lockup. The timer indicates if more then 10 µs have elapsed from the start of the EPP cycle (IOR
or IOW asserted) to BUSY being deasserted (after command). When a timeout occurs, the current EPP cycle
is aborted and the timeout condition is indicated in DSR bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be
in a write mode and the write signal to always be asserted.
write operation timing
The timing for a write operation (address or data) is shown in the timing diagram EPP write data or address cycle.
IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that
the write cycle can complete. The write cycle can complete under the following circumstances:
1. If the EPP BUSY is not ready (BUSY is active low) when AUTOFD or SELECTIN goes active, then the write
can complete when BUSY goes inactive high.
2. If the EPP BUSY is ready (BUSY is inactive high), then the chip must wait for it to go active low before
changing the state of AUTOFD, STROBE or SELECTIN. The write can complete once BUSY is determined
to be inactive.
write sequence of operation
The EPP mode write sequence of operations is as follows:
1. The host selects an EPP register, places data on the data bus, and drives IOW active.
2. The chip drives IOCHRDY inactive (low).
3. When BUSY is not asserted, the chip must wait until BUSY is asserted.
4. The chip places address or data on parallel data (PD) bus and asserts STROBE.
5. The chip asserts AUTOFD or SELECTIN indicating that the PD bus contains valid information, and the
STROBE signal is valid.
6. The peripheral device deasserts BUSY, indicating that any setup requirements have been satisfied and the
chip may begin the termination phase of the cycle.
7. The chip deasserts AUTOFD or SELECTIN which marks the beginning of the termination phase. If it has
not already done so, the peripheral should latch the information byte now. The chip latches the data from
the data bus for the parallel data (PD) bus and releases IOCHRDY allowing the host to complete the write
cycle.
8. The peripheral device asserts BUSY indicating to the host that any hold time requirements have been
satisfied and is acknowledging the termination of the cycle.
9. The chip may modify the STROBE and PD signals in preparation for the next cycle.
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