TL16PIR552 Datasheet, PDF (45/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 20. Extended Control Register (ECR)
Bit
Access
Name
Description
7–5
R/W
MODE
Bits 7–5 have the following selected modes of operation:
000: Standard Parallel Port mode (forward direction only)
001: Bidirectional Parallel Port mode
010: Parallel Port FIFO mode (forward direction only)
011: ECP Parallel Port mode
100: EPP mode
101: reserved
110: FIFO test mode
111: Configuration mode
4
R/W
ERRINTREN In ECP mode, when bit 4 is set to 0, an interrupt on the falling edge of FAULT is en-
abled. A 1 disables the interrupt.
3
R/W
DMAEN
When bit 3 is reset to 0, DMA is disabled. A bit setting of 1 enables the DMA. The
DMA starts when SERVICEINTR is reset to 0.
2
R/W
SERVICEINTR When bit 2 is set to 1, DMA and all service interrupts are disabled.
1
R
FULL
When bit 1 is set to 1, the FIFO is full.
0
R
EMPTY
When bit 0 is set to 1, the FIFO is empty.
CFIFO parallel port data FIFO
Bytes written or DMA transferred from the system to this FIFO are transmitted by a hardware handshake to the
peripheral using the standard parallel port protocol. This mode is only defined for the forward direction.
TFIFO test mode
Data bytes can be read, written, or DMA transferred to or from the system to this FIFO in any direction. Data
in the TFIFO register is not transmitted to the parallel port lines using a hardware protocol handshake. However,
data in the TFIFO may be displayed on the parallel port data lines. The TFIFO does not stall when overwritten
or underrun. Data is simply rewritten or overrun. The FULL and EMPTY bits must always keep track of the
correct FIFO state. The TFIFO transfers data at the maximum ISA rate so that software may generate
performance metrics.
The WRITEINTR threshold can be determined by starting with a full TFIFO, and emptying it one byte at a time
until the SERVICEINTR bit is set. This may generate a spurious interrupt, but indicates that the threshold has
been reached. Likewise, READINTR threshold can be determined by setting the direction bit to 1, and filling the
empty TFIFO a PWord at a time until SERVICEINTR bit is set. Data bytes are always read from the head of
TFIFO regardless of the value of the direction bit. For example, when a 0x4433, 0x2211, or a 0x00ff is written
to the FIFO, then reading the TFIFO returns a 0x4433, a 0x2211,or a 0x0ff in the same order in which it was
written. The FIFO size and interrupt threshold can be determined by writing PWords and checking the FULL
and SERVICEINTR bits.
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