TL16PIR552 Datasheet, PDF (17/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
IOR
(IOR RBR)
SINx
(first byte)
Stop
50%
Active
(see Note A)
Sample Clock
td7
(see Note A)
RXRDYx
50%
td8
50%
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Figure 10. Receiver Ready (RXRDY), FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(IOR RBR)
SINx
(first byte that reaches
the trigger level)
Sample Clock
td7
(see Note A)
RXRDYx
50%
50%
Active
(see Note A)
td8
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, td7 = 9 RCLKs.
Figure 11. Receiver Ready (RXRDY), FCR0 = 1 or FCR3 = 1 (Mode 1)
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