TL16PIR552 Datasheet, PDF (50/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
read operation timing
The timing for a read operation (data) is shown in Figure 20. IOCHRDY is driven active low at the start of each
EPP read and is released when it has been determined that the ready cycle can complete. The ready cycle can
complete under the following circumstances:
1. When the EPP bus is not ready (BUSY is active low when AUTOFD goes active) the read can complete
when BUSY goes inactive high.
2. When the EPP bus is ready (BUSY is inactive high) the chip must wait for it to go active low before changing
the state of STROBE or before AUTOFD goes active. The read can complete once BUSY is determined
inactive.
read sequence of operation
The read sequence is as follows:
1. The host selects an EPP register and drives IOR active.
2. The TL16PIR552 drives IOCHRDY inactive (low).
3. When BUSY is not asserted, the chip must wait until BUSY is asserted.
4. The PD bus is put into a high-impedence state and deasserts STROBE.
5. The TL16PIR552 asserts AUTOFD or SELECTIN indicating that the PD bus is in a high-impedence state,
DIR is set, and the STROBE signal is valid.
6. The peripheral device drives the PD bus valid.
7. A peripheral device deasserts BUSY, indicating that PD is valid and the TL16PIR552 may begin the
termination phase of the cycle.
8. The TL16PIR552 latches the data from the PD bus for the data(D) bus, deasserts AUTOFD or SELECTIN,
and this marks the beginning of the termination phase. The valid data is then driven onto the D bus and
asserts (releases) IOCHRDY allowing the host to complete the read cycle.
9. The peripheral device puts PD into a high-impedence state and asserts BUSY, indicating to the host that
PD is in a 3-state condition.
10. The chip may modify STROBE, DIR, and PD in preparation for the next cycle.
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