TL16PIR552 Datasheet, PDF (5/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
FAULT
25
I Fault indication. In compatibility mode FAULT is set high to acknowledge the 1284 mode requested. The
EPP mode is user defined. In ECP mode FAULT generates an error interrupt when asserted. It provides
a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP
mode the peripheral is permitted (but not required) to drive this terminal low to request a reverse transfer.
The request is merely a “hit” to the host; the host has ultimate control over the transfer direction. FAULT
is typically used to generate an interrupt to the host CPU.
GND
9, 30,
48, 53,
69
Ground terminal.
INIT
54
O Initiation. In compatibility mode INIT is pulsed low to reset the interface and force a return to the compatibility
mode idle phase.In ECP mode INIT is driven low to place the channel in the reverse direction and it allows
the peripheral to drive the bidirectional data lines when SELECTIN is high. In EPP mode INIT is active low.
When driven low, this signal initiates a termination cycle that results in the interface returning to the
compatibility mode.
INTRPT0,
INTRPT1
40,41
O Interrupt (0–1). When active (high), INTRPT0 or INTRPT1 informs the CPU that the UART has an interrupt
to be serviced. Four conditions that cause an interrupt to be issued include a receiver error, received data
is available, an empty transmitter holding register, or an enabled modem-status interrupt.
IOCHRDY
39
O ISA channel ready. IOCHRDY is an open drain output that extends the length of a bus cycle when it is
inactive.
IOR
14
I Read input. IOR is an active low input signal that enables the selected channel to output data to D7–D0.
The data output depends upon the register selected by the address A2–A0 inputs and chip select.
IOW
13
I Write input. IOW is an active low input signal that enables the data to be input to either a UART or to the
parallel port. The data destination depends upon the register selected by the address inputs A2–A0 and
chip select.
IRSIN0, IRSIN1 65, 78 I Serial data. IRSIN0 and IRSIN1 are serial inputs from an IR serial data communication device.
PD0–PD7
52–49, I/O Parallel data bits (0–7). PD0–PD7 provide a byte wide input or 47–44 output port to the system. These bits
47–44
contain address, data, or RLE command data.
PDACK
17
I Parallel port DMA acknowledge. PDACK is an active low input.
PDRQ
35
O DMA Request. PDRQ is used for parallel port DMA requests during ECP and FIFO modes.
PERROR
23
I Peripheral error. In compatibility mode PERROR is driven high when the device encounters an error in the
paper path. In ECP mode the peripheral drives PERROR low to acknowledge a reverse request (INIT).
Based on this signal the host determines when it is permitted to drive the data bus. In EPP mode the signal
is user defined.
PINTR
34
O Parallel port interrupt. PINTR is a 3-state output. In EPP mode this is an active high, positive-edge triggered
input.
PPCS
21
I Chip select. PPCS is used for the parallel port internal registers and is an active-low signal.
RI0,
67,80 I Ring Indicator. RI0 and RI1 are modem-status signals whose condition can be verified by reading bit 6 (RI)
RI1
of the MSR. Bit 2 (TERI) of the MSR indicates that the RI0/RI1 input has transitioned from a low to a high
level since the last read operation from MSR. If the modem-status interrupt is enabled when this transition
occurs, an interrupt is generated.
RESET
19
I Reset. RESET is an active high reset that when asserted, clears all UARTs and parallel port printer internal
registers.
RTS0,
RTS1
61
O Request to send. When active, RTS0 or RTS1 informs the modem or data set that the UART is ready to
72
receive data. RTS0 or RTS1 is set to its active level by setting the RTSx modem-control register bit and is
set to inactive (high) either as a result of master reset or during loop-mode operations or by resetting bit
1 (RTS) of the MCR. In the auto-RTS mode, RTSx is set to its inactive level by the receiver threshold-control
logic.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
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