TL16PIR552 Datasheet, PDF (40/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
parallel port (see Table 13)
The parallel port is essentially an extended capabilities port with an additional enhanced parallel port mode, and
includes the following features:
• Compatible with standard Centronics parallel interface
• Support for ECP and EPP
• Data path FIFO buffer
• Direct Memory Access (DMA) transfer
• Decompression of run length encoded data in ECP reverse mode
The parallel port is an extended capabilities parallel (ECP) port with additional enhanced parallel port (EPP)
protocol support. Modes 000 and 001 are compatible with Centronics and bidirectional Centronics ports, and
mode 100 is defined to be EPP mode. Thus, together with the ECP protocol modes, the parallel port supports
three distinct transfer protocols which all share the standard parallel port signals.
The parallel port consists of an 8-bit host interface (including DMA support) which is connected to the fast-AT
bus, a sequencer containing state-machines for the three different protocols, a 16-byte FIFO data path and a
parallel interface.
transfer protocols
There are three parallel port transfer protocols in the TL16PIR552. Descriptions of these protocols follow and
specifications with terminal numbers follow in Table 13.
standard Centronics protocol
In the standard Centronics modes, the parallel port is compatible with the Centronics unidirectional or
bidirectional parallel port. It consists of a single-byte data port which writes and reads data to/from the port data
lines and registers to control and reflect the status of the parallel port signals. Signaling protocol is handled by
software, which must assert control strobes and poll for acknowledgement itself.
enhanced parallel port (EPP protocol)
In enhanced parallel port mode, SELECTIN and AUTOFD are automatically generated and are redefined to be
address strobe and data strobe, respectively, while STROBE indicates a write or a read cycle. Additional I/O
addresses are defined for data and address accesses and when these locations are used, handshaking is
performed automatically by hardware.
extended capabilities port (ECP) protocol
The enhanced capability port specification is an enhancement to the IEEE 1284 standard; it defines new transfer
protocols and timing which offer a reverse channel as fast as the forward channel. Software overhead is reduced
by direct memory access (DMA) support, data buffering, and automatic strobe generation. ECP defines
separate I/O locations for address and data accesses.
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