TL16PIR552 Datasheet, PDF (16/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
SINx
Data Bits 5 – 8
Stop
Sample Clock
Trigger Level
INTRPTx
(FCR6, 7 = 0, 0)
INTRPTx
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
td7
(see Note A)
50%
50%
50%
td8
50%
td8
Active
50%
IOR
(RD RBR)
Active
50%
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Figure 8. Receive FIFO First Byte (Sets DR Bit)
(FIFO at or above
trigger level)
(FIFO below
trigger level)
SINx
Sample Clock
Timeout or
Trigger Level
Interrupt
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
Stop
td7
(see Note A)
50%
50%
td8
Top Byte of FIFO
50%
td7
td8
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active 50%
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
50%
Active
Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set)
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