TL16PIR552 Datasheet, PDF (26/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0
2
2
3
4
5
6
7
0 DLAB = 1 1 DLAB = 1
Receiver Transmitter
Interrupt-
FIFO
BIT
Buffer
NO. _Register
Holding
Register
Interrupt-
Enable
Ident.
Register
Control
Register
Line-
Control
Modem-
Control
(Read
(Write
Register
(Read
(Write
Register Register
Only)
Only)
Only)
Only)
Line-
Status
Register
Modem-
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Divisor
Latch
(MSB)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0 Data Bit 0† Data Bit 0
Enable
Received-
Data-
Available
Interrupt
(ERBI)
0 if
Interrupt
Pending
FIFO
Enable
Word-
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
(∆CTS)
Bit 0
Bit 0
Bit 8
Enable
Transmitter
Word-
Holding-
Interrupt Receiver
Length
Request
1
Data Bit 1
Data Bit 1
Register-
ID
FIFO
Select
to Send
Empty
Bit 1
Reset
Bit 1
(RTS)
Interrupt
(WLS1)
(ETBEI)
Overrun
Error
(OE)
Delta
Data-
Set
Ready
(∆DSR)
Bit 1
Bit 1
Bit 9
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line-Status
Interrupt
(ELSI)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
(an unused
internal
signal)
Parity
Error
(PE)
Trailing-
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
3
Data Bit 3
Data Bit 3
Enable
Modem-
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 3
(see
Note 6)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
Enable
external
interrupt
(INT0 or
INT1)
Framing
Error
(FE)
Delta
Data-
Carrier
Detect
(∆DCD)
Bit 3
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even-
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4
Bit 4
Bit 12
5
Data Bit 5
Data Bit 5
0
Autoflow Transmitter
Data
0
Reserved
Stick
Control
Holding
Set
Bit 5
Parity
Enable
Register
Ready
(AFE)
(THRE)
(DSR)
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(see
Note 6)
Receiver
Trigger
(LSB)
Break
Control
Transmitter
Ring
0
Empty
Indicator
Bit 6
(TEMT)
(RI)
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(see
Note 6)
Receiver
Trigger
(MSB)
Divisor-
Latch
Access
Bit
(DLAB)
0
Error in
RCVR
FIFO
(see
Note 4)
Data-
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
† _{Bit 0 is the least significant bit. It is the first bit serially transmitted or received.}
NOTE 6: These bits are always 0 in the TL16C450 mode. When DLAB = 1, the six least significant bits of the scratch register contain the prescaler
value. IR logic is selected if the seventh bit of the scratch register is set to 1. Otherwise UART output is selected.
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