TL16PIR552 Datasheet, PDF (32/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
Bit 2: Parity error (PE) indicator. When PE is set to 1, it indicates that the parity of the received data character
does not match the parity selected in the line control register (bit 4). PE is reset every time the CPU reads the
contents of the line status register. In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
Bit 3: Framing error (FE) indicator. When FE is set to 1, it indicates that the received character did not have a
valid (1) stop bit. FE is reset every time the CPU reads the contents of the line status register. In the FIFO mode,
this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the
CPU when its associated character is at the top of the FIFO. The UART tries to resynchronize after a framing
error. To accomplish this, it is assumed that the framing error is due to the next start bit. The UART samples
this start bit twice and then accepts the input data.
Bit 4: Break interrupt (BI) indicator. When BI is set to 1, it indicates that the received data input was held in the
logic low state for longer than a full-word transmission time. A full-word transmission time is defined as the total
time to transmit the start, data, parity, and stop bits. BI is reset every time the CPU reads the contents of the
line status register. In the FIFO mode, this error is associated with the particular character in the FIFO to which
it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break
occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to
the marking state for at least two RCLK samples and then receives the next valid start bit.
Bit 5: Transmitter holding-register-empty (THRE) indicator. THRE is set to 1 when the transmitter holding
register is empty, indicating that the UART is ready to accept a new character. If the THRE interrupt is enabled
when THRE is set to 1, an interrupt is generated. THRE is set to 1 when the contents of the transmitter holding
register are transferred to the transmitter shift register. THRE is reset to 0 concurrent with the loading of the
transmitter holding register by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is
cleared when at least one byte is written to the transmit FIFO.
Bit 6: Transmitter empty (TEMT) indicator. TEMT bit is set to 1 when the transmitter holding register and the
transmitter shift register are both empty. When either the transmitter holding register or the transmitter shift
register contains a data character, TEMT is reset to 0. In the FIFO mode, TEMT is set to 1 when the transmitter
FIFO and shift register are both empty.
Bit 7: In the TL16PIR552, this bit is always reset to 0. In the TL16C450, this bit is always a 0. In the FIFO mode,
LSR7 is set to 1 when there is at least one parity, framing, or break error in the FIFO. It is cleared when the
microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem status register (MSR)
The modem status register is an 8-bit register that provides information about the current state of the control
lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide
change information; when a control input from the modem changes state, the appropriate bit is set to 1. All four
bits are reset to 0 when the CPU reads the modem status register. The contents of this register are summarized
in Table 3 and are described in the following paragraphs.
Bit 0: Change in clear to send (∆ CTS) indicator. ∆ CTS indicates that the CTS input has changed state since
the last time it was read by the CPU. When ∆ CTS is set to 1 (autoflow control is not enabled and the modem
status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no
interrupt is generated.
Bit 1: Change in data set ready (∆ DSR) indicator. ∆ DSR indicates that the DSR input has changed state since
the last time it was read by the CPU. When ∆ DSR is set to 1 and the modem status interrupt is enabled, a modem
status interrupt is generated.
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