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TL16PIR552 Datasheet, PDF (29/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR) (continued)
Bit 1: When set to 1, bit 1 clears all bytes in the receiver FIFO and resets its counter logic to 0. The shift register
is not cleared. The one that is written to this bit position is self clearing.
Bit 2: When set to 1, bit 2 clears all bytes in the transmit FIFO and resets its counter to 0. The shift register is
not cleared. The one that is written to this bit position is self clearing.
Bit 3: When FCR0 is set to 1, setting FCR3 to a 1 causes RXRDY and TXRDY to change from a 0 to a 1.
Bits 4 and 5: These bits are reserved for future use.
Bits 6 and 7: These bits are used to set the trigger level for the receiver FIFO interrupt.
Table 5. Bits 6 and 7 FCR
BIT 7
0
0
1
1
BIT 6
0
1
0
1
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
01
04
08
14
line control register (LCR)
The system programmer controls the format of the asynchronous data-communication exchange through the
line-control register. In addition, the programmer is able to retrieve, inspect, and modify the contents of the
line-control register; this eliminates the need for separate storage of the line characteristics in system memory.
The contents of this register are summarized in Table 3 and described in the following paragraphs.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 6.
Table 6. Bits 0 and 1 LCR
BIT 1
0
0
1
1
BIT 0
0
1
0
1
WORD LENGTH
5 bits
6 bits
7 bits
8 bits
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