TL16PIR552 Datasheet, PDF (6/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
RXRDY0,
RXRDY1
42,43
O Receiver ready. Receiver direct-memory access (DMA) signaling is available with RXRDY0 or RXRDY1.
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control-register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode
0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least one character in the receiver
FIFO or receiver holding register, RXRDY0 and RXRDY1 are active (low). When RXRDYx has been active
but there are no characters in the FIFO or holding register, RXRDYx goes inactive (high). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDYx goes active (low);
when it has been active but there are no more characters in the FIFO or holding register, it goes inactive
(high).
SELECT
24
I Select. In compatibility mode SELECT is set high to indicate that the printer is on line. In ECP mode SELECT
indicates an affirmative response for each extensibility byte. It is high when the requested mode is
supported. In EPP mode the signal is user defined.
SELECTIN
55
O Select. In compatibility mode SELECTIN is set low by the host to select the peripheral device. It is set high
to request the 1284 mode. In ECP mode SELECTIN is driven high by the host. It is driven low by the host
to terminate the ECP mode and return to the compatibility mode. In EPP mode SELECTIN is an active low
output that is used to denote address read or write operations.
SIN0, SIN1
68,75 I Serial data. SIN0 and SIN1 are inputs from a connected communication device.
SOUT0,
SOUT1
59, 70 O Serial outputs. Either IR output format or UART output format. Composite serial data outputs are to be
connected to a communication device. SOUT0 and SOUT1 are set to the marking state (1) as a result of
a master reset operation.
STROBE
56
O Data strobe. In compatibility mode STROBE is set active low to transfer data into the input latch of the
peripheral device. Data is valid while STROBE is low. In ECP mode STROBE is used in a closed-loop
handshake with BUSY to transfer data or address information from the host to the peripheral device. In EPP
mode this signal is set low to denote an address or data write operation to the peripheral and is set high
to denote and address or data read operation from the peripheral.
TC
16
I Terminal count. TC is an active high input during DMA and when PDACK is low. TC indicates that the data
transfer is complete.
TEST
28
I Test. TEST is tied low during normal operation. To turn the oscillator off and measure ICCQ current, TEST
is tied active (high).
TXRDY0,
TXRDY1
32,33
O Transmitter ready. Transmitter DMA signaling is available with TXRDY0 and TXRDY1. When operating in
the FIFO mode, one of two types of DMA signalling can be selected through FCR3. When operating in the
TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between the CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple DMA transfers
are made continuously until the transmit FIFO has been filled.
VCC
18, 37,
58 62,
74
5-V supply voltage.
XIN
XOUT
29 I/O Crystal input and output terminals. A 22-MHz clock is required to meet the internal timing required by the
31
1284 parallel port (minimum 40 to 60% duty cycle).
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
detailed description
autoflow control
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTSx input must be active before
the transmitter FIFO can emit data (see Figure 1). With auto-RTS, RTSx becomes active when the receiver
needs more data and notifies the sending serial device (see Figure 1). When RTSx is connected to CTSx, data
transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated
when UART1 and UART2 are TL16PIR552s with enabled autoflow control. If not, overrun errors occur when
the transmit-data rate exceeds the receiver FIFO read latency.
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