TL16PIR552 Datasheet, PDF (46/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
description of printer operation
ECP: command/data
The ECP mode supports two advanced features to improve the effectiveness of the protocol for some
applications. The features are implemented by allowing the transfer of normal 8-bit data or 8-bit commands.
When in the forward direction, normal data is transferred when AUTOFD is high and an 8-bit command is
transferred when AUTOFD is low.
The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel
address.
When in the reverse direction, normal data is transferred when BUSY is high and an 8-bit command is
transferred when BUSY is low. The most significant bit of the command is always zero. Reverse channel
addresses are seldom used and may not be supported in hardware.
Table 21. Bits 6 and 7 of the ECP Command
D7
D6
0
Run-length count (0–127)
1
Channel Address (0–127)
run length encoded data compression
The parallel port supports decompression of run length encoded (RLE) data in ECP DMA mode (011) reverse
direction only. During reverse direction transfers, the peripheral indicates a command byte is to be transferred
by setting PERIPHACK (BUSY) low. Bits 6-0 of the command byte indicate the number of times the next data
byte should be replicated; bit 7 is always zero.
interrupts
The interrupts are enabled by the SERVICEINTR bit in the ECR register. When SERVICEINTR bit is a 1 the
DMA and all of the service interrupts are disabled. When SERVICEINTR bit is a 0 the selected interrupt condition
is enabled. When the interrupting condition is valid, then the interrupt is generated immediately when this bit
is changed from a 1 to a 0. This can occur during the programmed I/O when the number of bytes removed or
added from/to the FIFO does not cross the threshold.
The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing.
After a brief pulse low following the interrupt event, the interrupt line is put into a high-impedance state so that
other interrupts may assert.
An interrupt is generated:
1. For DMA transfers: When SERVICEINTR is 0, DMAEN is 1, and the DMA TC is received.
2. For programmed I/O:
a. When the SERVICEINTR bit is reset to 0, DMAEN is set to 0, DIRECTION is set 0, and there are 12
or more free bytes in the FIFO. Also, an interrupt is generated when SERVICEINTR bit is cleared to
0 whenever there are 12 or more free bytes in the FIFO.
b. When the SERVICEINTR bit is reset to 0, DMAEN is set to 0, DIRECTION is set to1 and there are 12
or more bytes in the FIFO. Also, an interrupt is generated when SERVICEINTR bit is cleared to 0
whenever there are 12 or more byte in the FIFO.
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