TL16PIR552 Datasheet, PDF (4/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
A0–A2
10–12 I Register select. A0–A2 are address lines that select the internal registers in the device.
ACK
27
I Data acknowledge. In compatibility mode ACK is pulled low by the peripheral device to acknowledge
transfer of a data byte from the host. In ECP mode, ACK is used in a closed loop handshake with the host
AUTOFD to transfer data from the peripheral device to the host. It is asserted low by the peripheral device
to indicate data is available. In EPP mode, ACK is used by the peripheral device to interrupt the host. This
signal is active high and is positive-edge triggered.
AUTOFD
57
O Autofeed. In compatibility mode AUTOFD is set low in conjunction with SELECTIN being set high to request
a 1284 mode. Then AUTOFD is set high after the peripheral device acknowledges the signal by setting ACK
low. In EPP mode, AUTOFD is an active low output that is used to denote data read or write operations.
It also provides a ninth data bit that is used to determine whether address or data information is present
on the data lines in the forward mode. In EPP mode this signal is active low to denote data read or write
operations. In ECP mode, AUTOFD requests a byte of data from the peripheral when asserted,
handshaking with ACK in the reverse direction. In the forward direction AUTOFD indicates whether the data
lines contain the ECP address or data. The host drives this signal to flow control in the reverse direction.
It is an “interlocked” handshake with ACK. AUTOFD also provides command information in the forward
phase.
BDO
38
O Bus buffer output. BDO output is active (high) when the CPU is not reading data. It controls the system bus
driver.
BUSY
26
I Busy. In compatibility mode BUSY is driven high to indicate that the peripheral is not ready to receive data.
In the ECP mode, BUSY is driven high to indicate that the peripheral is not ready to receive data and is
driven low to indicate that the peripheral is ready to receive data in forward mode. In reverse mode, BUSY
is low when the information on the data lines are commands (RLE) and it is high when the information on
the data lines is data. In EPP mode, BUSY is active low. It is driven inactive as a positive acknowledgment
from the peripheral device that data or address information is completed. It is active when the peripheral
is ready for the next data and address transfer. In ECP mode, BUSY deasserts to indicate that the peripheral
can accept data. It handshakes with STROBE in the forward direction. In the reverse direction BUSY
indicates whether the data lines contain the ECP command information or data. The peripheral uses this
signal to control flow in the forward direction. It is an “interlocked” handshake with STROBE. BUSY also
provides command information in the reverse direction.
CLK_OUT0,
CLK_OUT1
36, 73 O Prescaler Outputs. CLK_OUT0 and CLK_OUT1 drive the UARTs.
CS0, CS1
15,20
I Chip select. CS0 and CS1 are active low inputs that act as an enable for the write operation and a read
operation for the UART. CS0 enables UART0 and CS1 enables UART1.
CTS0,
CTS1
63
I Clear to send. CTS0 and CTS1 are modem-status signals whose condition can be verified by reading bit
79
4 (CTS) of the MSR. Bit 0 (∆CTS) of the MSR indicates that CTS0 or CTS1 has changed states since the
last read operation from the MSR. When the modem-status interrupt is enabled, CTS0 or CTS1 changes
states, and an interrupt is generated. CTS0 or CTS1 is also used in the auto-CTS mode to control the
transmitter.
D7–D0
1–8 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the CPU and the device.
DCD0,
DCD1
66
I Data carrier detect. DCD0 and DCD1 are modem status signals whose condition can be verified by reading
77
bit 7 (DCD) of the modem status register (MSR). Bit 3 (∆DCD) of the MSR indicates that DCD0 or DCD1
has changed state since the last read from MSR. If the modem status interrupt is enabled when DCD0 or
DCD1 changes state, an interrupt is generated.
DSR0,
DSR1
64
I Data set ready. DSR0 and DSR1 are modem status signals whose condition can be verified by reading bit
76
5 (DSR) of the MSR. Bit 1 (∆DSR) of the MSR indicates that DSR0 or DSR1 has changed state since the
last read from MSR. If the modem status interrupt is enabled when DSR0 or DSR1 changes state, an
interrupt is generated.
DTR0,
DTR1
60
O Data terminal ready. When active, (low), DTR0 or DTR1 informs a modem or data set that the UART is ready
71
to establish communication. DTR0 or DTR1 is placed in the active state by setting bit 0 of the modem-control
register (MCR) to 1. DTRx is placed in the inactive state either as a result of a master reset, during
loop-mode operation, or resetting bit 0 of the MCR.
ECPCS
22
I Chip select. ECPCS is used for the ECP parallel port internal registers, and is an active low signal.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
4
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