TL16PIR552 Datasheet, PDF (31/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
Bit 4 (LOOP) provides a local loop-back feature for diagnostic testing of the UART. When LOOP is set to 1, the
following occurs:
• The transmitter SOUT is set high.
• The receiver SIN is disconnected.
• The output of the transmitter shift register is looped back into the receiver shift-register input.
• The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
• The two modem control outputs (DTR, RTS) are internally connected to the four modem control inputs.
• The four modem control outputs are forced to the inactive (high) levels.
Bit 5 (AFE) is the autoflow control enable. When set high the autoflow control, as described in the detailed
description, is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit and receive data paths to the UART. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational, but the modem control interrupt sources are now the lower four
bits of the modem control register instead of the four modem control inputs. All interrupts are still controlled by
the interrupt enable register.
The UART flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
MCR BIT 5
(AFE)
1
1
0
Table 8. UART Flow
MCR BIT 1
(RTS)
1
0
X
UART FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
Auto-RTS and auto-CTS disabled
line status register (LSR)
The line status register provides information to the CPU concerning the status of data transfers. The contents
of this register are described below and summarized in Table 3. The line status register is intended for read
operations only; writing to this register is not recommended outside of a factory testing environment. Bits 1–4
are the error conditions that produce a receiver line status interrupt.
Bit 0: Data ready (DR) indicator for the receiver. DR is set to 1 whenever a complete incoming character has
been received and transferred into the receiver buffer register or the FIFO. DR is reset to 0 by reading all of the
data in the receiver buffer register or the FIFO.
Bit 1: Overrun error (OE) indicator. When OE is set to 1, it indicates that before the character in the receiver buffer
register was read, it was overwritten by the next character transferred into the register. OE is reset every time
the CPU reads the contents of the line status register. If the FIFO mode data continues to fill the FIFO beyond
the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in
the shift register is overwritten, but it is not transferred to the FIFO.
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