TL16PIR552 Datasheet, PDF (35/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled:
• FIFO timeout interrupt occurs when the following conditions exist:
– At least one character is in the FIFO.
– The most recent serial character was received more than four continuous character times ago (if
two stop bits are programmed, the second one is included in this time delay).
– The most recent microprocessor read of the FIFO occurred more than four continuous character
times ago. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.
• Character times are calculated by using the RCLK input for a clock signal that makes the delay
proportional to the baud rate.
• When a timeout interrupt has occurred, it is cleared and the timer is reset when the microprocessor
reads one character from the receiver FIFO.
• When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
• The occurrence of transmitter holding-register-empty interrupt (IIR(3–0) = 2) is delayed one character
time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at
the same time since the last time the transmitter FIFO was empty. It is cleared (IIR(3–0) = 1) as soon as
the transmitter holding register is written to (1 to 16 characters may be written to the transmit FIFO while
servicing this interrupt) or the IIR is read. The first transmitter interrupt after changing FCR is immediate
if it is enabled.
• The transmitter empty indicator (LSR6 (TEMT) = 1) is delayed one character time when there has not
been at least two bytes in the transmitter FIFO at the same time since the last time that TEMT = 1. TEMT
is set after the stop-bit has been completely shifted out (finishes one complete bit time or 16 BAUDOUT
cycles).
• The transmitter FIFO empty indicator (LSR5 (THRE) = 1) works the normal way in this mode and is not
delayed.
Character timeout and receiver FIFO trigger-level interrupts have the same priority as the current
received-data-available interrupt.
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