TL16PIR552 Datasheet, PDF (43/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
register definitions
Table 15 is a summary of the parallel port internal registers, assuming 378h is the base address.
Table 15. Parallel port internal register
Chip
Select
PPCS
ECPCS
A2–A0
000
000
001
010
011
100–111
000
000
Mode
Std/Bidi (000–001)
ECP (011)
All
All
EPP (100)
EPP (100)
ECP (011)
CFIFO (010)
000
TFIFO (110)
000
Config (111)
001
Config (111)
010
All
Access
R/W
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
Name
DATA
ECPAFIFO
DSR
DCR
EPPADDR
EPPDATA
ECPDFIFO
PP DATA
FIFO
TEST FIFO
CNFGA
CNFGB
ECR
Function
Data port
ECP address FIFO
Status register
Control register
EPP address port
EPP data Port
ECP data FIFO
Parallel port data FIFO
Configuration register A
Configuration register B
Extended control register
data register (DATA)
This is the standard parallel port data register. In standard mode, writing to this register drives data onto the
parallel port data lines. In all other modes, the drivers may be put into a high-impedance state by setting the
direction bit in the DCR. Reads to this register return the value of the data lines.
ECP address FIFO register (ECPAFIFO)
A data byte written to this register is placed in the FIFO and tagged as an ECP address. Table 16 is a summary
of the device status register bits and their descriptions. Table 17 is a summary of the device control register bits
and their descriptions.
Table 16. Device status register (DSR)
Bit
Default
Name
Description
7
Default
BUSY
Bit 7 corresponds to the inverse of a BUSY input
6
–
ACK
Bit 6 corresponds to the ACK input
5
–
PE
Bit 5 corresponds to the PERROR input
4
–
SLCT
Bit 4 corresponds to the SELECT input
3
–
ERR
Bit 3 corresponds to the FAULT input
2
–
PRINT
Print interrupt. Bit 2 is reset to 0 by the rising transition of ACK and set to 1 by a read
operation of this register.
1
0
–
Bit 1 is reserved
0
0
TIMEOUT When enabled in EPP mode, bit 0 is set to 1 when 10-µs timeout occurs. Bit 0 is cleared
by any write operation to the DSR register.
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