TL16PIR552 Datasheet, PDF (27/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The UART receiver section of the TL16PIR552 consists of a receiver shift register (RSR) and a receiver buffer
register (RBR). The RBR is actually a 16-byte FIFO. Timing is supplied by the 16× receiver clock (RCLK).
Receiver-section control is a function of the UART line-control register.
The UART RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the receiver buffer register and the
received-data-available interrupt is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when
the data is read out of the receiver buffer register. In the FIFO mode, the interrupts are generated based on the
control setup in the FIFO-control register.
transmitter holding register (THR)
The UART transmitter section of the TL16PIR552 consists of a transmitter holding register (THR) and a
transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Transmitter-section control is a function
of the UART line-control register.
The UART THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the
transmitter holding-register-empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO-control register.
interrupt enable register (IER)
The interrupt-enable register enables each of the five types of interrupts (refer to Table 4) and INTRPT in
response to an interrupt generation. The interrupt-enable register can also be used to disable the interrupt
system by setting bits 0 through 3 to logic 0. The contents of this register are summarized in Table 3 and are
described below.
Bit 0: When set to 1, bit 0 enables the received-data-available interrupt
Bit 1: When set to 1, bit 1 enables the transmitter holding-register-empty interrupt
Bit 2: When set to 1, bit 2 enables the receiver line-status interrupt
Bit 3: When set to 1, bit 3 enables the modem-status interrupt
Bits 4 through 7: These bits are not used (always set to 0)
interrupt identification register (IIR)
The UART has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The UART provides four prioritized levels of interrupts:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character timeout
Priority 3 – Transmitter holding-register empty
Priority 4 – Modem status (lowest priority)
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