TL16PIR552 Datasheet, PDF (36/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO polled mode operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), resetting IER0, IER1, IER2, IER3, or all four to 0 puts
the UART in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
• LSR0 is set as long as there is one byte in the receiver FIFO.
• LSR (1 – 4) specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the transmitter holding register is empty.
• LSR6 indicates that both the transmitter holding register and transmitter shift register are empty.
• LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO-polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters (See Table 11 and 12).
Table 11. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
DIVISOR USED
TO GENERATE
16 × CLOCK
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
PERCENT OF ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
BAUD RATES
0.026
0.058
0.69
2.86
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