TL16PIR552 Datasheet, PDF (30/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is reset to 0, one stop bit is generated in the data. When bit 2 is set to 1, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7.
BIT 2
0
1
1
1
1
Table 7. Bit 2 LCR
WORD LENGTH SELECTED
BY BITS 1 AND 2
Any word length
5 bits
6 bits
7 bits
8 bits
NUMBER OF STOP
BITS GENERATED
1
1 1/2
2
2
2
Bit 3: Parity enable bit. When bit 3 is set to 1, a parity bit is generated in transmitted data between the last
data-word bit and the first stop bit. In received data, when bit 3 is set to 1, parity is checked. When bit 3 is reset
to 0, no parity is generated or checked.
Bit 4: Even parity select bit. When parity is enabled by bit 3, a 1 in bit 4 produces even parity (an even number
of 1s in the data and parity bits) and a 0 in bit 4 produces odd parity (an odd number of 1s).
Bit 5: Stick parity bit. When bits 3, 4, and 5 are set to 1s, the parity bit is transmitted and checked as a 0. When
bits 3 and 5 are 1s and bit 4 is a 0, the parity bit is transmitted and checked as 1. When bit 5 is a 0, stick parity
is disabled.
Bit 6: Break control bit. Bit 6 is set to 1 to force a break condition; i.e., a condition where SOUT is forced to the
spacing (0) state. When bit 6 is reset to 0, the break condition is disabled and has no effect on the transmitter
logic; it only affects SOUT.
Bit 7: Divisor latch access bit (DLAB). Bit 7 must be set to 1 to access the divisor latches of the baud generator
during a read or write. Bit 7 must be reset to 0 during a read or write to access the receiver buffer, the transmitter
holding register, or the interrupt-enable register.
modem control register (MCR)
The modem control register is an 8-bit register that controls an interface with a modem, data set, or peripheral
device that is emulating a modem. The contents of this register are summarized in Table 3 and are described
in the following paragraphs.
Bit 0 (DTR) controls the DTR output.
Bit 1 (RTS) controls the RTS output.
Bit 2 Has no effect on operation.
Bit 3 When MCR3 is set, the external serial channel interrupt is enabled.
When any of bits 0-3 is set to 1, the associated output is forced low; a bit value of 0 forces the associated output
high.
30
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265