TL16PIR552 Datasheet, PDF (25/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB† A2
A1
A0
REGISTER
0
L
L
L Receiver buffer (read), transmitter holding register (write)
0
L
L
H Interrupt enable
X
L
H
L Interrupt identification (read only)
X
L
H
L FIFO control (write)
X
L
H
H Line control
X
H
L
L Modem control
X
H
L
H Line status
X
H
H
L Modem status
X
H
H
H Scratch
1
L
L
L Divisor latch (LSB)
1
L
L
H Divisor latch (MSB)
† _{The divisor-latch access bit (DLAB) is the most significant bit of the line-control register. The DLAB}
signal is controlled by writing to this bit location (see Table 4).
accessible registers
The system programmer, using the CPU, has access to and control over any of the UART registers that are
summarized in Table 2. These registers control UART operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 2. UART Reset Functions
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem-status changes)
RTS
DTR
Scratch Register
Divisor-Latch (LSB and MSB) Registers
Receiver Buffer Register
Transmitter Holding Register
RCVR FIFO
XMIT FIFO
RESET CONTROL
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR/MR
Read RBR/MR
Read IR/Write THR/MR
Read MSR/MR
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
MR/FCR1 – FCR0/∆FCR0
MR/FCR2 – FCR0/∆FCR0
RESET STATE
All bits low (0 – 3 forced and 4 – 7 permanent)
Bit 0 is high, bits 1, 2, 3, 6, and 7 are low, and bits 4 – 5 are
permanently low
All bits low
All bits low
All bits low (6 – 7 permanent)
Bits 5 and 6 are high; all other bits are low
Bits 0 – 3 are low; bits 4 – 7 are input signals
High
Low
Low
Low
Low
High
High
No effect
No effect
No effect
No effect
All bits low
All bits low
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