TL16PIR552 Datasheet, PDF (41/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 13. Parallel Port Connector Specifications
Terminal
Number
Standard
EPP
ECP
56
STROBE
WRITE
HOSTCLK
52-49, 44-47 PD0–7
PD0–7
PD0–7
27
ACK
INTR
PERIPHCLK
26
BUSY
WAIT
PERIPHACK
23
PERROR
USER DEFINED
MPERIPHREQUEST
24
SELECT
USER DEFINED
USER DEFINED
57
AUTOFD
DSTRB
HOSTACK
25
FAULT
USER DEFINED
PERIPHREQUEST
54
INIT
INIT
REVERSEREQUEST
55
SELECTIN
ASTRB
SELECTIN(1,3)
NOTE 7: For the cable interconnection required for ECP support and the slave connector terminal
numbers, refer to the Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan.
7, 1993. This document is available from Microsoft®.
parallel port modes of operation (see Table 14)
The seven parallel port operating modes are selected by bits 7-15 of the extended control register.
1. Standard Centronics mode (000)
This is the default mode in which the parallel port behavior is compatible with the Centronics standard port. The
FIFO is reset and the direction bit in the device control register has no effect.
2. Bidirectional Centronics standard mode (001)
This is the same as mode 000 except that setting the direction bit puts the data line in a high-impedance state
and reading the data register returns the value on the data lines.
3. Parallel port FIFO mode (010)
In this mode bytes written or DMA transferred to the FIFO are transmitted automatically using the Centronics
standard protocol. Only the forward direction is useful.
4. ECP mode (011)
In the forward direction (direction = 0) data written to the ECPDFIFO and bytes written to ECPAFIFO addresses
are placed in a single FIFO and transmitted automatically using ECP protocol. In the reverse direction
(direction = 1) data bytes are transferred from the ECP parallel port and placed in the ECPDFIFO.
5. Enhanced parallel port mode (100)
In this mode, EPP read, write, or address/data cycles can be executed or, if no EPP cycle is pending, compatible
Centronics standard access can be made (as in mode 001). Note that the software must ensure that the
direction = 0 before attempting to perform an EPP write cycle.
6. FIFO test mode (110)
In this mode the FIFO can be written and read or DMA transferred in any direction, but no data will be transmitted
on the parallel port. The FIFO does not stop accepting or sending data when full or empty conditions occur; FIFO
read and write address counters will wrap.
7. Configuration mode (111)
In this mode the CONFGA and CONFGB registers are accessible.
Microsoft is a registered trademark of Microsoft Corporation.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
41