TL16PIR552 Datasheet, PDF (28/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
When an interrupt is generated, the interrupt identification register indicates that an interrupt is pending and
encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are
summarized in Table 2 and described in Table 4. Detail on each bit is as follows:
Bit 0: Used either in a hardware-prioritized or polled-interrupt system. When this bit is a reset to 0, an
interrupt is pending; for a 1, no interrupt is pending.
Bits 1 and 2: The bits are used to identify the highest priority interrupt pending as indicated in Table 3
Bit 3: This bit is always 0 in the TL16C450 mode. In FIFO mode, this bit is set along with bit 2 to indicate that a
timeout interrupt is pending.
Bits 4 through 5: These bits are not used (always reset at 0).
Bits 6 and 7: These bits are always reset to 0 in the TL16C450 mode. They are set when bit 0 of the
FIFO-control register is equal to 1.
Table 4. Interrupt-Control Functions
INTERRUPT-
IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
PRIORITY
LEVEL
INTERRUPT TYPE
None
1
None
Receiver line status
2
Received data available
2
Character time-out
indication
3
Transmitter holding-
register empty
4
Modem status
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
None
None
Overrun error, parity error,
framing error, or break interrupt
Read the line-status register
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode
Read the receiver buffer
register
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time
Read the receiver buffer
register
Transmitter holding-register
empty
Read the interrupt-
identification register (if source
of interrupt) or writing into the
transmitter holding register
Clear to send, data-set ready,
ring indicator, or data-carrier
detect
Read the modem-status
register
FIFO control register (FCR)
The FIFO control register (FCR) is a write-only register at the same location as the IIR, which is a read-only
register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of
DMA signaling (see Table 5).
Bit 0: When set to 1, bit 0 enables the transmitter and receiver FIFOs. This bit must be set to 1 when other FCR
bits are written to or they are not programmed. Changing this bit clears the FIFOs.
28
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265