TL16PIR552 Datasheet, PDF (47/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
3. When ERRINTREN is 0 and FAULT transitions from 1 to 0 or when ERRINTREN is reset from 1 to 0 and
FAULT is asserted, an interrupt is generated.
4. When the ACKINTEN is 1 and the ACK signal transitions from 0 to 1, an interrupt is generated.
FIFO operation
When the FIFO threshold is set to 12 all data transfers to or from the parallel port can proceed in the DMA or
programmed I/O (non-DMA) mode is indicated by the selected mode. The FIFO is used by selecting the parallel
port FIFO mode or ECP parallel port mode. After a reset, the FIFO is disabled. Each data byte is transferred
by a programmed I/O cycle or PDRQ depending on the selection of DMA or programmed I/O mode.
DMA transfers
DMA transfers are always to or from the ECPDFIFO, TFIFO or CFIFO registers. DMA utilizes the standard PC
DMA transfers, the host first sets up the direction and state as in the programmed I/O case. It then programs
the DMA controller in the host with the desired count and memory address. DMAEN is set to 1 and
SERVICEINTR is reset to 0. The ECP requests the DMA transfers from the host by activating the PDRQ
terminal. The DMA empties or fills the FIFO using the appropriate direction and mode. When the terminal count
in the DMA controller is reached, an interrupt is generated and SERVICEINTR is asserted, disabling the DMA.
The FIFO is enabled directly by asserting PDACK and addresses need not be valid. PINTR is generated when
a TC is received. (Note: The only way to properly terminate DMA transfers is with a TC request.)
The DMA may be disabled in the middle of a transfer by first disabling the host DMA controller and setting
SERVICEINTR to 1, followed by resetting DMAEN to 0, and waiting for the FIFO to become empty or full.
Reasserting the DMA is accomplished by enabling DMA in the host, setting DMAEN to 1, followed by resetting
SERVICEINTR to 0.
DMA mode - transfers from the FIFO to the host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO when it runs out of transfer data,
even when the chip continues to request more data from the peripheral.)
The ECP activates the PDRQ terminal when there is data in the FIFO. The DMA controller must respond to the
request by reading data from the FIFO. The ECP deactivates the PDRQ terminal when the FIFO is empty or
when the TC becomes true (qualified by PDACK), indicating that no more data is required. PDRQ goes inactive
after PDACK goes active for the last byte of the data transfer (or on the active edge of IOR, on the last byte,
if no edge is present on PDACK). When PDRQ goes inactive due to the FIFO going empty, then PDRQ is active
again as soon as there is one byte in the FIFO. When PDRQ goes inactive due to the TC, then PDRQ is active
again when there is one byte in the FIFO, and SERVICEINTR has been re-enabled. (Note: A data underrun may
occur when PDRQ is not removed in time to prevent an unwanted cycle.)
interrupt programmed I/O mode or non-DMA mode
The ECP or parallel port FIFOs may also be operated using interrupt-driven programmed I/O.
Programmed I/O transfers are to the ECPDFIFO and ECPAFIFO or from the ECPDFIFO or to/from the TFIFO
at 400h. To use the programmed I/O transfers, the host first sets up the direction and state, resets DMAEN to
0 and resets SERVICEINTR to 0.
The programmed I/O empties or fills the FIFO using the appropriate direction and mode.
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