TL16PIR552 Datasheet, PDF (48/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
programmed I/O - transfers from the FIFO to the host
In the reverse direction an interrupt occurs when the SERVICEINTR bit is 0 and 12 bytes are available in the
FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise 12 bytes may be
read from the FIFO in a single burst.
An interrupt is generated when the SERVICEINTR bit is 0 and the number of bytes in the FIFO is greater than
or equal to 12. The PINTR terminal can be used for interrupt-driven systems. The host must respond to the
request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO.
If at this time the FIFO is full, it can be completely emptied in a single burst. Otherwise, a minimum of 12 bytes
may be read from the FIFO in a single burst.
programmed I/O - transfers from the host to the FIFO
In the forward direction an interrupt occurs when SERVICEINTR = 0 and there are 12 or more byte spaces free
in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be
re-read. Otherwise, it may be filled with 12 bytes.
An interrupt is generated when the SERVICEINTR bit is 0 and the number of bytes in the FIFO is less than or
equal to 4. The PINTR terminal can be used for interrupt-driven systems. The host must respond to the request
by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst. Otherwise,
a minimum of 12 bytes may be written to the FIFO in a single burst. This process is repeated until the last byte
is transferred into the FIFO.
48
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265