TL16PIR552 Datasheet, PDF (12/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
parallel-port EPP data or address write cycle timing requirements over recommended ranges of
supply voltage and operating free-air temperature
PARAMETER
th6
Hold time, BUSY↓ to PD invalid
td28 Delay time, IOW↓ to PD valid
td29 Delay time, BUSY↓ to STROBE↑
td30 Delay time, STROBE↓ to AUTOFD↓
td31 Delay time, BUSY↑ to AUTOFD↑
td32 Timeout, IOW↓ to BUSY↑
td33 Delay time, SELECTIN↑ to BUSY↓
td34 Delay time, IOW↓ to IOCHRDY↓
td35 Delay time, BUSY↑ to IOCHRDY↑
td36 Delay time, IOCHRDY↑ to IOW↑
td37 Delay time, IOW↓ to STROBE↓
td38 Delay time, IOW↑ to IOW or IOR↓
td39 Delay time, BUSY↓ to STROBE↓
FIGURE
21
21
21
21
21
21
21
21
21
21
21
21
21
MIN
60
10
60
0
60
10
200
0
60
30
0
60
20
MAX
140
30
100
10
100
12
25
120
40
40
UNITS
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
parallel-port EPP data or adress read cycle timing requirements over recommended ranges of
supply voltage and operating free-air temperature
PARAMETER
th7
Hold time, AUTOFD, SELECTIN↑ to PD hi-Z
th8
Hold time, IOR↑ to D hi-Z (Hold Time)
td40 Delay time, BUSY↑ to AUTOFD, SELECTIN↑
td41 Delay time, AUTOFD, SELECTIN↓ to PD Valid
td42 Delay time, IOR↓ to IOCHRDY↓
td43 Delay time, BUSY↑ to IOCHRDY↑
td44 Delay time, PD valid to D valid
td45 Timeout, IOR↓ to BUSY↑
td46 Delay time, IOR↑ to IOW or IOR↓
td47 Delay time, IOCHRDY↑ to IOR↑
FIGURE
22
22
22
22
22
22
22
22
22
22
MIN
10
0
120
110
0
80
0
10
60
30
MAX
20
200
25
130
25
12
UNITS
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
parallel-port FIFO timing requirements over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
tsu3 Setup time, PD valid to STROBE↓
th9
Hold time, PD hold from STROBE↑
tw5
Pulse duration, STROBE pulse width low
td48 Delay time, STROBE↓ to BUSY↑ active
td49 Delay time, BUSY↓ to STROBE↓
FIGURE
23
23
23
23
23
MIN
550
500
500
600
MAX
125
UNITS
ns
ns
ns
ns
ns
12
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