TL16PIR552 Datasheet, PDF (34/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
prescaler descriptions: (continued)
When DLAB = 1, the six least significant bits of the scratch register contain the prescaler value.
Table 10. SCR (0–5) Values
SCR(0-5) Value (Hex)
0 (0)
0.5 (1)
1 (2)
1.5 (3)
2 (4) to 31.5 (3F)
Result
No Clock (high)
divide-by-1
divide-by-1
divide-by-1
divide by 2 to 31.5
programmable baud generator
The UART contains a programmable baud generator that takes a clock input in the range between dc and 16
MHz and divides it by a divisor in the range between 1 and 2¹⁶ –1. The output frequency of the baud generator
is 16 times (16×) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When
either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 5 and 6 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz,
respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (refer to Figure 16 for examples of typical
clock circuits).
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
• The received-data-available interrupt issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
• The IIR receive-data-available indication also occurs when the FIFO-trigger level is reached, and like
the interrupt, it is cleared when the FIFO drops below the trigger level.
• The receiver line-status interrupt (IIR = 06) has higher priority than the received-data-available (IIR =
04) interrupt.
• The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver
FIFO. It is reset when the FIFO is empty.
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