TL16PIR552 Datasheet, PDF (44/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 17. Device Control Register (DCR)
Bit
Default
Name
Description
7
1
–
This bit is reserved
6
1
–
This bit is reserved
5
0
DIR
In standard and CFIFO modes this bit has no effect; in all other modes, when set to 1
this bit put the parallel port data lines into a high-impedance state, 0 = forward, 1 = re-
verse.
4
0
INT2EN When high, this bit enables interrupts to access the host (on the rising edge of ACK).
3
0
SLIN
1: SELECT output active;
0: SELECT output inactive.
2
0
INIT
0: INIT output active;
1: INIT output inactive.
1
0
AFD
1: AUTOFD output active;
0 AUTOFD output inactive.
0
0
STB
1: STROBE output active;
0: STROBE output inactive.
EPP address register (EPPADDR)
This is the EPP address strobe register. In EPP mode, an address strobe is automatically generated when data
is read from or written to this register. This register is only available in EPP mode.
EPP data register (EPPDATA)
This is the EPP data strobe register. In EPP mode, a data strobe is automatically generated when data is read
or written to this register. This register is only available in EPP mode.
ECP Data FIFO register (ECPDFIFO)
A data byte wirtten or DMA transferred to this register is placed in the FIFO and tagged as ECP data in forward
direction. Data bytes from peripherals are read under an automatic hardware handshake from ECP into this
FIFO when the direction bit is set to 1. Table 18 is a description of the bits in the ECP configuration, register A.
Table 19 is a description of the bits in the ECP configuration, register B. Table 20 is a description of the bits in
the extended control register.
Table 18. ECP Configuration Register A (CNFGA)
Bit
Name
Description
7–4
IMPLD
Bits 7–4 are used for the implementation ID number. Always read as 0001, 8-bit implementation (PWord =
1 byte)
3–0
–
These bits are reserved; read as 1s
Table 19. Configuration Register B (CNFGB)
Bit
Name
Description
7
COMPRESS Bit 7 always read as a 0: Compression is not supported
6
INTRVALUE Bit 6 returns value on IRQ line to determine possible conflicts
5–3
INTRLINE Bits 5–3 are always read as 001: IRQ7 selected
2–0
DMACHNL Bits 2–0 are always read as 011: DMA channel 3 selected
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