TL16PIR552 Datasheet, PDF (10/52 Pages) Texas Instruments – DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT

TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
tcR Cycle time, read (tw7 + td8)
tcW Cycle time, write (tw6 + td5)
tw1 Pulse duration, IOW
tw2 Pulse duration, IOR
tw3 Pulse duration, RESET
tsu1 Setup time, data valid before IOW↑
tsu2 Setup time, CTS↑ before midpoint of stop bit
th1 Hold time, CS valid after IOW↑
th2 Hold time, address valid after IOW↑
th3 Hold time, data valid after IOW↑
th4 Hold time, chip select valid after IOR↑
th5 Hold time, address valid after IOR↑
td1 Delay time, CS valid before IOW↓
td2 Delay time, address valid before IOW↓
td3 Delay time, CS valid to IOR↓
td4 Delay time, address valid to IOR↓
td5 Delay time, IOR↓ to data valid
td6 Delay time, IOR↑ to floating data
ALT. SYMBOL
RC
WC
tWR
tRD
tMR
tDS
tWCS
tWA
tDH
tRCS
tRA
tCSW
tAW
tCSR
tAR
tRVD
tHZ
FIGURE
5
6
5
16
5
5
5
6
6
5
5
6
6
6
6
TEST CONDITIONS
CL = 75 pF
CL = 75 pF
MIN MAX UNIT
65
ns
59
ns
50
ns
50
ns
1
µs
20
ns
10 ns
15
ns
15
ns
15
ns
20
ns
20
ns
10
ns
13
ns
10
ns
13
ns
20
ns
10
ns
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 5)
PARAMETER
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
td7
Delay time, stop to INTRPTx↑ or read RBR↑ to
LSI INTRPT↑ or stop to RXRDY↓
tSINT
7, 8, 9,
10, 11
1
RCLK
cycle
td8
Delay time, read RBR/INTRPT or read to RXRDY↑
or IOR↑ to INTRPTx↓
tRINT
7, 8, 9,
10, 11
CL = 75 pF
70 ns
NOTE 5: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt-
identification register or line-status register).
10
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265