CC2510_15 Datasheet, PDF (69/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
Note that after the Debug Lock bit has
changed due to a Flash Information Page write
or a flash mass erase, a HALT, RESUME,
DEBUG_INSTR,
STEP_INSTR,
or
STEP_REPLACE command must be executed
so that the Debug Lock value returned by
READ_STATUS shows the updated Debug
Lock value. For example a dummy NOP
DEBUG_INSTR command could be executed.
The Debug Lock bit will also be updated after
a device reset so an alternative is to reset the
chip and reenter debug mode.
The CHIP_ERASE command will set all bits in
flash memory to 1. This means that after
issuing a CHIP_ERASE command the boot
sector will be writable, no pages will be write-
protected, and all debug commands are
enabled.
The lock protect bits are written as a normal
flash write to FWDATA (see Section 12.3.2), but
the Debug Interface needs to select the Flash
Information Page first instead of the Flash
Main Page which is the default setting. The
Information Page is selected through the
Debug Configuration which is written through
the Debug Interface only. Refer to Section
11.4.1 and Table 46 for details on how the
Flash Information Page is selected using the
Debug Interface.
Table 44 defines the byte containing the flash
lock protection bits. Note that this is not an
SFR, but instead the byte stored at location
0x000 in Flash Information Page.
Bit Field Name Description
7:5
Reserved, write as 0
4
BBLOCK
Boot Block Lock
0
Page 0 is write protected
1
Page 0 is writeable, unless LSIZE is 000
3:1 LSIZE[2:0] Lock Size. Sets the size of the upper flash area which is write-protected. Byte sizes are listed below
000 32 KB (all pages)
001 24 KB
CC2510F32 and CC2511F32 only
010 16 KB
CC2510F32 and CC2511F32 only
011 8 KB
CC2510F32 and CC2511F32 only
100 4 KB
CC2510F32 and CC2511F32 only
101 2 KB
CC2510F32 and CC2511F32 only
110 1 KB
CC2510F32 and CC2511F32 only
111 0 bytes (no pages)
0
DBGLOCK Debug lock bit
0
Disable debug commands
1
Enable debug commands
Table 44: Flash Lock Protection Bits Definition
11.4 Debug Commands
The debug commands are shown in Table 45.
Some of the debug commands are described
in further detail in the following sections
11.4.1 Debug Configuration
The commands WR_CONFIG and
RD_CONFIG are used to access the debug
configuration data byte. The format and
description of this configuration data is shown
in Table 46
11.4.2 Debug Status
A debug status byte is read using the
READ_STATUS command. The format and
description of this debug status is shown in
Table 47.
The READ_STATUS command is used e.g.
for polling the status of flash chip erase after a
CHIP_ERASE command or oscillator stable
status required for debug commands HALT,
RESUME, DEBUG_INSTR, STEP_REPLACE,
and STEP_INSTR.
SWRS055G
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