CC2510_15 Datasheet, PDF (217/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
0xDF16: BSCFG - Bit Synchronization Configuration
Bit Field Name
Reset R/W Description
7:6 BS_PRE_KI[1:0] 01
5:4 BS_PRE_KP[1:0] 10
3 BS_POST_KI
1
2 BS_POST_KP
1
1:0 BS_LIMIT[1:0]
00
R/W The clock recovery feedback loop integral gain to be used before a sync word
is detected (used to correct offsets in data rate):
00 KI
01 2KI
10 3KI
11 4KI
R/W The clock recovery feedback loop proportional gain to be used before a sync
word is detected
00 KP
01 2KP
10 3KP
11 4KP
R/W The clock recovery feedback loop integral gain to be used after a sync word is
detected.
0 Same as BS_PRE_KI
1 KI /2
R/W The clock recovery feedback loop proportional gain to be used after a sync
word is detected.
0 Same as BS_PRE_KP
1 KP
R/W The saturation point for the data rate offset compensation algorithm:
00 ±0 (No data rate offset compensation performed)
01 ±3.125% data rate offset
10 ±6.25% data rate offset
11 ±12.5% data rate offset
SWRS055G
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