CC2510_15 Datasheet, PDF (155/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
U0UCR (0xC4) - USART 0 UART Control
Bit Field Name Reset R/W Description
7
FLUSH
0
R0/ Flush unit. When set to 1, this event will immediately stop the current operation
W1 and return the unit to idle state.
This bit will be 0 when returning from PM2 and PM3
6
FLOW
0
R/W UART 0 hardware flow control enable. Selects use of hardware flow control with
RTS and CTS pins
0 Flow control disabled
1 Flow control enabled
5
D9
0
R/W UART 0 data bit 9 contents. This value is used when 9 bit transfer is enabled.
When parity is disabled the value written to D9 is transmitted as the 9^th bit when
BIT9=1.
If parity is enabled then this bit sets the parity level as follows.
0 Even parity
1 Odd parity
4
BIT9
0
R/W UART 0 9-bit data enable
0 8 bits transfer
1 9 bits transfer (content of the 9^th bit is given by D9 and PARITY.)
3
PARITY
0
R/W UART 0 parity enable
0 Parity disabled
1 Parity enabled
2
SPB
0
R/W UART 0 number of stop bits
0 1 stop bit
1 2 stop bits
1
STOP
1
R/W UART 0 stop bit level
0 Low stop bit
1 High stop bit
0
START
0
R/W UART 0 start bit level. The polarity of the idle line is assumed to be the opposite of
the selected start bit level.
0 Low start bit
1 High start bit
SWRS055G
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