CC2510_15 Datasheet, PDF (38/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
Component
Value
C301
1 µF ± 10%, 0402 X5R
C203/C214
33 pF ± 5%, 0402 NP0
C202
56 pF
C212
10 nF
C213
33 pF
C201/C211
27 pF ± 5%, 0402 NP0
C231, C241
100 pF ± 5%, 0402 NP0
C171, C181
15 pF ± 5%, 0402 NP0
C232, C242
1.0 pF ± 0.25 pF, 0402 NP0
C233
1.8 pF ± 0.25 pF, 0402 NP0
C234
1.5 pF ± 0.25 pF, 0402 NP0
L231, L232, L241 1.2 nH ± 0.3 nH, 0402 monolithic
L281
470 nH ± 10%
R271
56 kΩ ± 1%, 0402
R264
1.5 kΩ ± 1%
R262/R263
33 Ω ± 2%
X1
26.0 MHz surface mount crystal
X2
32.768 kHz surface mount crystal (optional)
X3
48.0 MHz surface mount crystal (fundamental)
X4
48.0 MHz surface mount crystal (3^rd overtone)
Manufacturer
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata GRM1555C series
Murata LQG-15 series
Murata LQM18NNR47K00
Koa RK73 series
Koa RK73 series
Koa RK73 series
NDK, AT-41CD2
Epson MC-306 Crystal Unit
Abracon ABM8 series
Table 29: Bill Of Materials for the CC2510Fx/CC2511Fx Application Circuits (subject to changes)
9.7 PCB Layout Recommendations
The top layer should be used for signal routing,
and the open areas should be filled with
metallization connected to ground using
several vias.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance and sufficiently low inductance to
ground. In the CC2510EM reference designs
[1] 9 vias are placed inside the exposed die
attached pad. These vias should be “tented”
(covered with solder mask) on the component
side of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
See Figure 13 for top solder resist and top
paste masks recommendations.
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. The best routing is from
the power line to the decoupling capacitor and
then to the CC2510Fx supply pin. Supply power
filtering is very important.
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via. Direct connections between
neighboring power pins will increase noise
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface mount devices are highly
recommended. Please note that components
smaller than those specified may have differing
characteristics.
Schematic, BOM, and layout Gerber files are
all available from the TI website for both the
CC2510EM reference design [1] and the
CC2511 USB Dongle reference design [2].
SWRS055G
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