CC2510_15 Datasheet, PDF (45/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
Register
Name
SFR
Module
Address
ADCCON1 0xB4
ADC
ADCCON2 0xB5
ADC
ADCCON3 0xB6
ADC
ADCL
0xBA
ADC
ADCH
0xBB
ADC
RNDL
0xBC
ADC
RNDH
0xBD
ADC
ENCDI
0xB1
AES
ENCDO
0xB2
AES
ENCCS
0xB3
AES
DMAIRQ
0xD1
DMA
DMA1CFGL 0xD2
DMA
DMA1CFGH 0xD3
DMA
DMA0CFGL 0xD4
DMA
DMA0CFGH 0xD5
DMA
DMAARM 0xD6
DMA
DMAREQ 0xD7
DMA
FWT
0xAB
FLASH
FADDRL
0xAC
FLASH
FADDRH
0xAD
FLASH
FCTL
0xAE
FLASH
FWDATA
0xAF
FLASH
P0IFG
0x89
IOC
P1IFG
0x8A
IOC
P2IFG
0x8B
IOC
PICTL
0x8C
IOC
P1IEN
0x8D
IOC
P0INP
0x8F
IOC
PERCFG
0xF1
IOC
ADCCFG
0xF2
IOC
P0SEL
0xF3
IOC
P1SEL
0xF4
IOC
P2SEL
0xF5
IOC
P1INP
0xF6
IOC
P2INP
0xF7
IOC
P0DIR
0xFD
IOC
P1DIR
0xFE
IOC
P2DIR
0xFF
IOC
MEMCTR 0xC7
MEMORY
SLEEP
0xBE
PMC
Description
CC2510Fx / CC2511Fx
Retention⁶
ADC Control 1
ADC Control 2
ADC Control 3
ADC Data Low
ADC Data High
Random Number Generator Data Low
Random Number Generator Data High
Encryption/Decryption Input Data
Encryption/Decryption Output Data
Encryption/Decryption Control and Status
DMA Interrupt Flag
DMA Channel 1 - 4 Configuration Address Low
DMA Channel 1 - 4 Configuration Address High
DMA Channel 0 Configuration Address Low
DMA Channel 0 Configuration Address High
DMA Channel Arm
DMA Channel Start Request and Status
Flash Write Timing
Flash Address Low
Flash Address High
Flash Control
Flash Write Data
Port 0 Interrupt Status Flag
Port 1 Interrupt Status Flag
Port 2 Interrupt Status Flag
Port Pins Interrupt Mask and Edge
Port 1 Interrupt Mask
Port 0 Input Mode
Peripheral I/O Control
ADC Input Configuration
Port 0 Function Select
Port 1 Function Select
Port 2 Function Select
Port 1 Input Mode
Port 2 Input Mode
Port 0 Direction
Port 1 Direction
Port 2 Direction
Memory System Control
Sleep Mode Control
Y
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
[7:1]Y, [1:0]N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
[6:2]Y, [7,1:0]N
6 _{Registers without retention are in their reset state after PM2 or PM3. This is only applicable for}
registers / bits that are defined as R/W
SWRS055G
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