CC2510_15 Datasheet, PDF (166/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
0xDF45: I2SSTAT - I²S Status Register
Bit
Field Name Reset R/W Description
7
TXUNF
0
6
RXOVF
0
5
TXLR
0
4
RXLR
0
3
TXIRQ
0
2
RXIRQ
0
1:0
WCNT[9:8] 00
R/W
R/W
R
R
R/W1
H0
R/W1
H0
R
TX buffer underflow. This bit must be cleared by software
Rx buffer overflow. This bit must be cleared by software
0 Left channel should be placed in transmit buffer
1 Right channel should be placed in transmit buffer
0 Left channel currently in receive buffer
1 Right channel currently in receive buffer
TX interrupt flag. This bit is cleared by hardware when the I2SDATH register is
written.
0 Interrupt not pending
1 Interrupt pending
RX Interrupt flag. This is cleared by hardware when the I2SDATH register is read.
0 Interrupt not pending
1 Interrupt pending
Upper 2 bits of the 10-bit internal word counter at the time of the last trigger
0xDF46: I2SCLKF0 - I²S Clock Configuration Register 0
Bit
Field Name Reset R/W
Description
7:0
DENOM[7:0] 0x93 R/W
The clock division denominator low bits
0xDF47: I2SCLKF1 - I²S Clock Configuration Register 1
Bit
Field Name Reset R/W Description
7:0
NUM[7:0]
0xE2 R/W Clock division numerator low bits
0xDF48: I2SCLKF2 - I²S Clock Configuration Register 2
Bit Field Name
Reset R/W Description
7
DENOM[8]
6:0 NUM[14:8]
0
R/W
0x04 R/W
Clock division denominator high bits
Clock division numerator high bits
SWRS055G
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