CC2510_15 Datasheet, PDF (31/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
8.1 CPU and Peripherals
The 8051 CPU core is a single-cycle 8051-
compatible core. It has three different memory
access buses (SFR, DATA and
CODE/XDATA), a debug interface, and an
extended interrupt unit servicing 18 interrupt
sources. See Section 10 for details on the
CPU.
The memory crossbar/arbitrator is at the
heart of the system as it connects the CPU
and DMA controller with the physical
memories and all peripherals through the SFR
bus. The memory arbitrator has four memory
access points, access at which can map to
one of three physical memories on the
CC2510Fx and one of four physical memories
on the CC2511Fx: a 1/2/4 KB SRAM, 8/16/32 KB
flash memory, RF/I²S registers, and USB
registers (CC2511Fx). The memory arbitrator is
responsible for performing arbitration and
sequencing between simultaneous memory
accesses to the same physical memory.
The SFR bus is drawn conceptually in the
block diagram as a common bus that connects
all hardware peripherals, except USB, to the
memory arbitrator. The SFR bus also provides
access to the radio registers and I²S registers
in the radio register bank even though these
are indeed mapped into XDATA memory
space.
The 1/2/4 KB SRAM maps to the DATA
memory space and part of the XDATA and
CODE memory spaces. The memory is an
ultra-low-power SRAM that retains its contents
even when the digital part is powered off (PM2
and PM3).
The 8/16/32 KB flash block provides in-circuit
programmable non-volatile program memory
for the device and maps into the CODE and
XDATA memory spaces. Table 27 shows the
available devices in the CC2510/CC2511
family. The available devices differ only in
flash memory size. Writing to the flash block is
performed through a Flash Controller that
allows page-wise (1024 byte) erasure and 2-
byte-wise reprogramming. See Section 12.3
for details.
Device
CC2510F8
CC2511F8
CC2510F16
CC2511F16
CC2510F32
CC2511F32
Flash [KB]
8
8
16
16
32
32
Table 27: CC2510/CC2511 Flash Memory Options
A versatile five-channel DMA controller is
available in the system. It accesses memory
using a unified memory space and has
therefore access to all physical memories.
Each channel is configured (trigger event,
priority, transfer mode, addressing mode,
source and destination pointers, and transfer
count) with DMA descriptors anywhere in
memory. Many of the hardware peripherals
rely on the DMA controller for efficient
operation (AES core, Flash Controller,
USARTs, Timers, and ADC interface) by
performing data transfers between a single
SFR address and flash/SRAM. See Section
12.5 for details.
The interrupt controller services 18 interrupt
sources, divided into six interrupt groups, each
of which is associated with one out of four
interrupt priorities. An interrupt request is
serviced even if the device is in PM1, PM2, or
PM3 by bringing the CC2510Fx/CC2511Fx back to
active mode.
The debug interface implements a proprietary
two-wire serial interface that is used for in-
circuit debugging. Through this debug
interface it is possible to perform an erasure of
the entire flash memory, control which
oscillators are enabled, stop and start
execution of the user program, execute
supplied instructions on the 8051 core, set
code breakpoints, and single step through
instructions in the code. Using these
techniques it is possible to perform in-circuit
debugging and external flash programming.
See Section 10 for details.
The I/O-controller is responsible for all
general-purpose I/O pins. The CPU can
configure whether peripheral modules control
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