CC2510_15 Datasheet, PDF (114/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
T1CC0
T1CCn
0x0000
0: Set output on compare
1: Clear output on compare
2: Toggle output on compare
3: Set output on compare-up,
clear on compare down
4: Clear output on compare-up,
set on compare-down
5: Set when T1CCn,
clear when T1CC0
6: Clear when T1CCn,
set when T1CC0
T1CCn T1CC0 T1CCn
T1CCn T1CC0 T1CCn
Figure 34: Output Modes, Timer Up/Down Mode
12.6.6 Timer 1 Interrupts
There is one interrupt vector assigned to the
timer. This is T1 (Interrupt #9, see
Table
39). The following timer events may generate
an interrupt request:
• Counter reaches terminal count value
(overflow) or turns around on zero
• Input capture event
• Output compare event
The register bits T1CTL.OVFIF,
T1CTL.CH0IF,
T1CTL.CH1IF,
and
T1CTL.CH2IF contains the interrupt flags for
the terminal count value event (overflow), and
the three channel compare/capture events,
respectively. These flags will be asserted
regardless off the channel n interrupt mask bit
(T1CCTLn.IM). The CPU interrupt flag,
IRCON.T1IF will only be asserted if one or
more of the channel n interrupt mask bits are
set to 1. An interrupt request is only generated
when the corresponding interrupt mask bit is
SWRS055G
Page 114 of 236