CC2510_15 Datasheet, PDF (179/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
0xDE0D: USBFRMH - Current Frame Number (High byte)
Bit Field Name
Reset R/W Description
7:3
2:0 FRAME[10:8]
-
R0 Not used
000
R
3 MSB of 11-bit frame number
0xDE0E: USBINDEX - Current Endpoint Index Register
Bit Field Name
Reset R/W Description
7:4
3:0 USBINDEX[3:0]
-
0000
R0 Not used
R/W Endpoint selected. Must be set to value in the range 0 – 5
0xDE10: USBMAXI - Max. Packet Size for IN Endpoint{1 - 5}
Bit Field Name
Reset R/W Description
7:0 USBMAXI[7:0]
0x00
R/W Maximum packet size in units of 8 bytes for IN endpoint selected by
USBINDEX register. The value of this register should correspond to the
wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint.
This register must not be set to a value grater than the available FIFO
memory for the endpoint.
0xDE11: USBCS0 - EP0 Control and Status (USBINDEX=0)
Bit Field Name
Reset R/W Description
7 CLR_SETUP_END 0
6 CLR_OUTPKT_RDY 0
5 SEND_STALL
0
4 SETUP_END
0
3 DATA_END
0
2 SENT_STALL
0
1 INPKT_RDY
0
0 OUTPKT_RDY
0
R/W Set this bit to 1 to de-assert the SETUP_END bit of this register. This bit will be
H0 cleared automatically.
R/W Set this bit to 1 to de-assert the OUTPKT_RDY bit of this register. This bit will
H0 be cleared automatically.
R/W Set this bit to 1 to terminate the current transaction. The USB controller will
H0 send the STALL handshake and this bit will be de-asserted.
R
This bit is set if the control transfer ends due to a premature end of control
transfer. The FIFO will be flushed and an interrupt request (EP0) will be
generated if the interrupt is enabled. Setting CLR_SETUP_END=1 will de-
assert this bit
R/W This bit is used to signal the end of a data transfer and must be asserted in
H0 the following three situations:
1 When the last data packet has been loaded and USBCS0.INPKT_RDY is
set to 1
2 When the last data packet has been unloaded and
USBCS0.CLR_OUTPKT_RDY is set to 1
3 When USBCS0.INPKT_RDY has been asserted without having loaded
the FIFO (for sending a zero length data packet).
The USB controller will clear this bit automatically
R/W This bit is set when a STALL handshake has been sent. An interrupt request
H1 (EP0) will be generated if the interrupt is enabled This bit must be cleared
from firmware.
R/W Set this bit when a data packet has been loaded into the EP0 FIFO to notify
H0 the USB controller that a new data packet is ready to be transferred. When
the data packet has been sent, this bit is cleared and an interrupt request
(EP0) will be generated if the interrupt is enabled.
R
Data packet received. This bit is set when an incoming data packet has been
placed in the OUT FIFO. An interrupt request (EP0) will be generated if the
interrupt is enabled. Set CLR_OUTPKT_RDY=1 to de-assert this bit.
SWRS055G
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