CC2510_15 Datasheet, PDF (235/245 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory,2.4 GHz RF Transceiver, and USB Controller

CC2511F8 - Not Recommended for New Designs
CC2510Fx / CC2511Fx
Revision
SWRS055F
Date
2008.07.11
SWRS055G 2013.02.20
Description/Changes
- Changed description of T1CCTL1.MODE bit.
- UxGDR changed to UxGCR several places in the document
- Changed FREQ2.FREQ[21:16] reset value from 11110 to 011110
- Added changes to the DEVIATN register, and added also info regarding the same register to
section 13.9.1 and 13.9.2
- 12.14.2.2: Changed description of the UxCSR.ACTIVE bit
- 12.8: Added note stating that the Sleep timer should not be used in active mode. This info
has in earlier edition only been available in section 8.1
- Table 11: Text changed from “For operation in the range 24 - 26 MHz, please refer to Table
4 for Operating Conditions” to “For operation below 26 MHz, please refer to Table 4 for
Operating Conditions”
- Added section 9.4: Reference Signal
- Table 57 and Table 58: Fsck changed to Fs
- 12.8.1: WOREVT1 = desired event0; changed to WOREVT1 = desired event0 >> 8;
- Table 39: Added footnote saying that the Sleep Timer compare interrupt has additional
interrupt mask bits and interrupt flags found in its SFRs
- Updated Figure 26
- Changed the description of PKTSTATUS.SFD
- MCSM0.FS_AUTOCAL=1 changed to MCSM0.FS_AUTOCAL=01 and MCSM0.FS_AUTOCAL=0
changed to MCSM0.FS_AUTOCAL=00 throughout the document
- 13.1: Added note about SIDLE strobe
- Table 16, Table 71, and Section 13.17: Changed the state transition timing
- 13.10.3: Added reference to DN505 [12] regarding RSSI response time.
- Changes made to the description of I2SCFG0.ULAWE and I2SCFG0.ULAWC
- Section 13.9 and 13.9.2 and MDMCFG2 register: Added info saying that Manchester
encoding/decoding should not be used when using MSK modulation.
- Table 11: Changes done to the condition/note on Power Down Guard Time
- Added Section 6.11.1 (info regarding the RESET_N pin being sensitive to noise)
- Changes made to the ADCCON1 register.
- Changes made to Section 12.11.2.1 regarding how to generate pseudo-random bytes.
- Section 13.3.1.1: Added note explaining how the RFTXRXIF flag should be cleared when it
is not cleared by HW.
- The drive strength for I/O pins in output mode is not controlled by the PICTL register but by
IOCFG1.GDO_DS. This has been changes several places in the data sheet.
- Removed the Sleep Timer trigger for the DMA since the Sleep Timer should not be used in
active mode.
- Section 13.12.1: Added note regarding RSSI response time when using
MCSM1.RXOFF_MODE=11
- Changed the description of the T2CTL.INT field
- Several changes added throughout the document regarding calibration of the two RC
oscillators
- Added info several places in the document stating that the I²S interface will have
precedence in cases where other peripherals (except for the debug interface) are configured
to be on the same location even if the pins are configured to be general purpose I/O pins.
- QLP36 / QLP 36 replaced by QFN 36
- 12.8.2: Changes made to the description on how entering PM{0 - 2}, updating EVENT0, and
resetting the sleep timer should be done with respect to the 32 kHz clock source.
- Replaced Figure 6
Updated package and ordering information to RHH package.
SWRS055G
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